Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Breakfast Bytes

Memory and Storage: the Wall is Coming Down

It was MemCon this week. Three keynotes, three parallel tracks each with four presentations…

• 4 min read
IP , Memory , MemCon , storage , DRAM , flash memory

Breakfast Bytes

Rules for Radicals: Practical Advice for Adopting Formal

This year's Jasper User Group conference finished up with a dose of realism in a…

• 4 min read
Jasper User Group , JUG , formal , PMC Sierra , Imagination , Jasper , broadcom , Qualcomm , Paul's Posts , Formal verification

Whiteboard Wednesdays

Whiteboard Wednesdays—Automotive IP Subsystems

In this week's Whiteboard Wednesdays video, Charles Qi takes a closer look at IP…

• less than a min read
Automotive , Whiteboard Wednesdays , IP , subsystem

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Symbol Editor? 16.6 Has a Couple of New Enhancements…

The Allegro PCB Editor release has a few new capabilities related to symbol pins…

• 1 min read
Allegro GUI , Allegro 16.6 , SPB , PCB Editor , PCB design , Grzenia , Allegro PCB Editor , library , Allegro

SoC and IP

Cadence Ports LPDDR4/DDR4 Combo PHY to TSMC 28HPC to Serve Rapid Adoption in Consumer…

Rapid consumer product revolution continues to be enabled by semiconductor technology…

• 1 min read
DDR4 , LPDDR4 , MemCon , LPDDR , DDR , DDR3 , LPDDR3

Breakfast Bytes

Batterygate, the Scandal that Isn't

If you think power isn’t important then you must have been living under a rock for…

• 5 min read
Apple , Samsung , TSMC , Paul's Posts , power

Breakfast Bytes

Thanks for the Memory: How MemCon Got Started

It is MemCon on Tuesday. I talked to David Lin to find out how it all started. He…

• 3 min read
DDR2 , Memory , DDR4 , MemCon , flash , JEDEC , NAND flash , ddrx , DRAM , nor flash , DDR3

Breakfast Bytes

Weekly News, October 9th, 2015

TSMC and Samsung Both in iPhone 6s It emerged that for the Apple iPhone 6s and…

• 2 min read
Intel , 5nm test chip , Altera , imec , PMC-Sierra , iPhone 6s

Breakfast Bytes

Jasper: the Gold Standard for Formal Verification

It was the Jasper User Group JUG this week. I first went to JUG several years ago…

• 4 min read
Jasper User Group , JUG , Jasper , Paul's Posts , Formal verification

SoC and IP

USB Developer Days – Turning Specifications into Applications

Each time I start working on an introductory paragraph for a new USB blog entry,…

• 2 min read
USB 3.0 , cadence , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Breakfast Bytes

Cadence and imec Announce World's First 5nm Tapeout

7nm is already passé it seems! Today Cadence and imec announced the tapeout of the…

• 4 min read
testchip , imec , Innovus , 5nm , 7nm , SAQP , EUV

Breakfast Bytes

The Beginning of Breakfast Bytes

Yes, it’s true. The Cadence gravitational field finally pulled me back and I am now…

• 1 min read
Paul McLellan , DAC , Jasper User Group , VSLI

Whiteboard Wednesdays

Whiteboard Wednesdays—New Tensilica Vision P5 DSP

In this week's Whiteboard Wednesday video, Dennis Crespo highlights the performance…

• less than a min read
security , Automotive , DSP , Vision P5 , Whiteboard Wednesdays , IP , Tensilica , mobile

SoC and IP

Ethernet Reaches into Ever More Application Spaces

I blog from time to time about what’s new in Ethernet. I have just returned from…

• 2 min read
HDD , 802.3bs , Automotive Ethernet , Ethernet , Design IP and Verification IP , Ethernet PHYs

Whiteboard Wednesdays

Whiteboard Wednesdays—Meeting Automotive Memory and I/O Bandwidth Challenges

In this week's Whiteboard Wednesdays video, Charles Qi continues his discussion focused…

• less than a min read
Automotive , I/O , Whiteboard Wednesdays , IP , Memory , interfaces , bandwidth , high performance

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Pastemask DRC? 16.6 Has Several New Enhancements…

The Allegro PCB Editor 16.6 Pastemask to Pastemask DRC now checks the ‘Package Geometry…

• less than a min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

SoC and IP

Cadence Announces the First MIPI I3C Verification IP!

The MIPI Alliance has developed dozens of specifications, standardizing all interfaces…

• 1 min read
Verification IP , MIPI Alliance , MIPI , Design IP and Verification IP

Whiteboard Wednesdays

Whiteboard Wednesdays - A Peek Inside Future Automotive Networks

In this week's Whiteboard Wednesdays video, Charles Qi explains future automotive…

• less than a min read
Whiteboard Wednesdays , automotive engineering , Automotive Ethernet , automotive electronics , automotive IP

Life at Cadence

Cadence Celebrates Women’s Day in India

Cadence India celebrated Women’s Day across all four sites on March 9th. Women’s…

• less than a min read
Insights on Culture , inclusion , Women's Day , HeforShe , Cadence India
CDNS - Fix Layout Hompage