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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

SoC and IP

Cadence ONFI 4.0 Flash Memory IP Increases Data Access to 800Mtps and Reduces Power…

Announcing Availability of ONFI 4.0 IP Flash memory applications have expanded…

• 2 min read
QSPI , flash , ONFI , USB , SD , eMMC , ip cores , ECC

System, PCB, & Package Design 

Manage Your Shapes with Ease in the Latest 16.6 ISR of Cadence APD and SiP Layou…

Shapes. Whether it’s a split plane, a power ring or flag under your die, or a cavity…

• 4 min read
IC Packaging and SiP Design , Cadence Design Systems , bounding shapes , Digital SiP design , degassing , 16.6 , beta tools , package design , SiP Layout , shapes , application modes

System, PCB, & Package Design 

What's Good About Allegro PCB Editor DRC by Window? It’s in the 16.6 Release!

The 16.6 Allegro PCB Editor ‘DRC by Window’ command is an alternative to running…

• 1 min read
PCB , Cadence Design Systems , Allegro GUI , Allegro 16.6 , electrical constraints , SPB , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays—More on Camera Subsystems

In this week's Whiteboard Wednesdays video, the second in a three-part series, Pulin…

• less than a min read
blocks , Whiteboard Wednesdays , IP , subsystem , intellectual protocol , Tensilica , camera

Verification

Double-Take: Improving Validation Test Suite with System-Level, Coverage-Driven …

Application Spotlight When Freescale wanted to measure the coverage of their validation…

• 2 min read
validation test suite , Freescale , Coverage-Driven Verification , Palladium XP , verification

Whiteboard Wednesdays

Whiteboard Wednesdays - LPDDR4 for Automotive Memory

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty discusses why LPDDR4…

• less than a min read
Automotive , Whiteboard Wednesdays , IP , Memory , LPDDR4

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Disable of Open Space Routing? 16.6 Has It!

By default, the 16.6 Allegro PCB Editor ‘Add Connect’ command generates routes when…

• 1 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , Routing , SPB , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

Verification

Make Your Debugging Faster by Recording Your Simulator

One of the famous quotes of Brian Kernighan is: "Debugging is twice as hard as writing…

• 4 min read
Specman , debug , e , specman elite , simulation , verification

Whiteboard Wednesdays

Whiteboard Wednesdays—Extending a Processor’s Instruction Set

In this week’s Whiteboard Wednesdays video, Chris Rowen explains the benefits of…

• less than a min read
performance , Whiteboard Wednesdays , IP , instruction set , Chris Rowen , Tensilica , energy

SoC and IP

USB Type-C Interoperability Workshop—True, Real-Life Validation

There’s no denying that USB Type-C is the fastest adopted specification in the history…

• 1 min read
USB Type-C , DisplayPort , Alternate Mode

Verification

Use Model Versatility Is Key for Emulation Returns on Investment

It is always great to see when customers confirm what we in product management put…

• 4 min read
ROI , use models , Emulation , DAC 2015 , System Design and Verification

Digital Design

Hot Summer for the High-Level Synthesis Community

Summer is usually a slow time of the year due to vacations, beautiful weather, and…

• 4 min read
High-Level Synthesis , DAC 2015 , SystemC , Brian Bailey , HLS , SystemC Japan 2015

Whiteboard Wednesdays

Whiteboard Wednesdays—Understanding Camera Subsystems

In this week's Whiteboard Wednesdays video, Pulin Desai provides an overview of a…

• less than a min read
security , Automotive , Whiteboard Wednesdays , IP , subsystem , Tensilica , camera , mobile , PCI Express , intellectual property

Verification

Extending the e Language with Anonymous Methods

We're happy to have guest blogger Thorsten Dworzak describe how he added anonymous…

• 8 min read
Functional Verification , Ruby , anonymous methods , e language

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Embedded Cavity DRCs? It's NEW in the 16.6 Release…

Max cavity size and max cavity component count were offered as reports in the 16…

• 1 min read
PCB , Routing , 16.6 , High Speed , SPB , PCB Editor , Layout , Grzenia , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays—Specialty Memories

In this week's Whiteboard Wednesdays video, Lou Ternullo takes a closer look at what…

• less than a min read
Whiteboard Wednesdays , Memory , wide i/o , HMC , HBM

SoC and IP

Call for Papers for MemCon Closes This Friday

You still have a chance to get a paper accepted at the premier conference for memory…

• less than a min read
MemCon , memory technology , ip cores , memories

System, PCB, & Package Design 

BGA Ball Map Creation

Are you responsible for the creation and management of a BGA ball map or a die bump…

• 1 min read
Co-Design , IC package design , I/O planning , BGA ball map

Verification

Performance and the Use of Port mvl Lists (or, Nothing in Life is Free…)

When connecting to the DUT signals, we usually refer to the values as 0s or 1s. But…

• 4 min read
performance , Specman , Functional Verification , Incisive , e , e language
CDNS - Fix Layout Hompage