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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Verification

Doing Away With the Docking Station

My docking station with the rat’s nest of wires dangling from behind it could be…

• 2 min read
USB 3.0 , Verification IP , Docking station , Tensilica Design and Verification IP , VIP , DisplayPort , USB , power delivery , USB3.0 , USB 2.0 , Type-C , USB connector , Alternate Mode , USB 3.1

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Snake Router? The 16.6-2015 Release Has Several…

With the 16.6-2015 Allegro PCB Editor release, the Snake pattern router can be enabled…

• 3 min read
PCB , PCB Layout and routing , Allegro 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

Breakfast Bytes

Economic Uncertainty, the Global Economy and Semiconductors

The Monday before SEMICON West starts, there are two events that run in parallel…

• 4 min read
semi/gartner symposium , semicon west , gartner , semi , hilltop economics , Breakfast Bytes

Analog/Custom Design

IEEE Recognition of Cadence Software at DAC 2016

Cadence was awarded with the IEEE Donald O. Pederson Best Paper Award—EDA’s most…

• less than a min read
best paper award , DAC , Virtuoso , IEEE

Whiteboard Wednesdays

Whiteboard Wednesdays—Applying Deep Learning to Our Daily Lives

In this week's Whiteboard Wednesdays video, Samer Hijazi discusses bringing deep…

• less than a min read
Whiteboard Wednesdays , IP , deep learning , Samer Hijazi , Tensilica , embedded

Breakfast Bytes

Linley Mobile Conference...and That ARM Deal

This year's Linley Mobile and Wearables Conference is coming up next week on July…

• 4 min read
softbank , Linley , Linley Mobile & Wearables Conference , ARM , Breakfast Bytes

SoC and IP

PCI Express Trends and News at PCI-SIG 2016

PCI-SIG Developers Conference 2016 is now history, taking place at the Santa Clara…

• 1 min read
PCIe Gen4 , 10G-KR , SerDes , PCI Express

Breakfast Bytes

Softbank Buys ARM for $32B

Over the weekend it seems that Softbank has closed a deal to acquire ARM Holdings…

• 4 min read
softbank , Mobile World Congress , ARM , sprint

Breakfast Bytes

The Future of Neural Networks...and Our Robot Overlords

Chris Rowen, the CTO of the Cadence IP group, wrapped up the recent seminar in Las…

• 4 min read
open datasets , training , neural networks , data scientist , privacy , CNN , Breakfast Bytes

Academic Network

Meet the Winners of Tensilica Xtensa Embedded DSP Design Contest India 2016

The winners of the Tensilica Xtensa Embedded DSP Design Contest have been announced…

• 1 min read
Cadence Academic Network , Bangladesh , Tensilica , Xtensa Design Contest , India

Breakfast Bytes

Hierarchical Neural Networks

The German Traffic Sign Benchmark actually has the signs divided into groups: speed…

• 3 min read
neural networks , CNN , hierarchical neural networks

Verification

Fine Tuning of Coverage Model Definition

Functional Coverage is one of the main means to measure the quality and progress…

• 8 min read
funtional verification , Specman , coverage , Functional Verification , Coverage-Driven Verification , CDV , e , e language , Funcional Verification , team specman , Verification IP modeling , metric-driven verification , MDV

Academic Network

Cadence Academic Network in Poland

Poland is a country with long tradition in microelectronics education and research…

• 2 min read
university , Cadence Academic Network , Poland , university program

Academic Network

PRIME and SMACD Conferences in Lisbon

Cadence Academic Network is supporting for years PRIME (PhD Research in Microelectronics…

• 2 min read
Cadence Academic Network , academic workshop , ADE , Virtuoso

Breakfast Bytes

How to Optimize Your CNN

Convolutional neural nets (CNNs) are not programmed in the traditional sense, but…

• 4 min read
Low Power , cnn training , cnn optimization , neural networks , CNN , embedded neural nets

Academic Network

Students from Pohang University of Science and Technology Visit Cadence Headquar…

My team recently had the privilege of hosting first year undergraduate students aka…

• 1 min read
Cadence Academic Network

Academic Network

DAC: A Glimpse of the Future Innovators

Hope you read my previous blog on Cadence Academic Network sponsoring all the student…

• 1 min read
DAC , Cadence Academic Network

Whiteboard Wednesdays

Whiteboard Wednesdays - Gauging Signal Quality Using Eye Diagrams

In this week's Whiteboard Wednesdays video, Chung Huang summarizes his presentation…

• less than a min read
Whiteboard Wednesdays , eye diagrams , signal quality

Breakfast Bytes

Power-Efficient Recognition Systems for Embedded Applications

Neural networks are hot. Las Vegas is hot, too. And there is a connection. In late…

• 4 min read
Chris Rowen , training , neural networks , CNN , embedded
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