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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Breakfast Bytes

Why Do Layout Designers Say "Stream Out"?

For the same reason we "hang up" our phones. When a layout designer saves a design…

• 6 min read
GDSII , Stream Out , Layout , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—DUT Verification with Cadence VIP

In this week's Whiteboard Wednesday's video, Arindam Guha explains how to quickly…

• less than a min read
DUT verification , Verification IP , Whiteboard Wednesdays , VIP

SoC and IP

Will USB Type-C Connector Replace the 3.5mm Audio Jack?

In the past few days, there have been many posts on the Internet around Apple planning…

• 1 min read
USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , Design IP and Verification IP , USB connector , USB 3.1

Breakfast Bytes

Virtuoso: Advance to 10nm, If You Pass Go Collect $200

There are two major discontinuities in the last couple of process nodes—FinFETs and…

• 5 min read
EAD , FinFets , iPVS , Custom Routing , multi-patterning , Virtuoso , 10nm , modgens , color-aware layout , Breakfast Bytes

System, PCB, & Package Design 

Take Tighter Control Over Your Shape Degassing Patterns with Cadence 16.6 Allegro…

With metal density and balancing requirements getting stricter with every year that…

• 6 min read
Cadence Design Systems , SiP Design , 16.6 , IC package design , APD , Allegro Package Designer , manufacturing , SiP Layout , shapes

Breakfast Bytes

TSMC 3D. Red and Green Glasses Not Required

I have been taking a look at TSMC's 3D packaging technologies. From numerous presentations…

• 4 min read
CoWoS , 3DIC , info-pop , TSMC , InFO , info_s , Breakfast Bytes

Breakfast Bytes

Can You Pass As a Brit? Just Answer 3 Simple Questions

It’s Thankgiving! Happy Thanksgiving if you are reading this on the day. Cadence…

• 9 min read
thanksgiving , lbw , guy fawkes , gunpowder plot , glorious revolution , marmite

Breakfast Bytes

Voltus-Fi: Faithful Custom and Analog EMIR and Power Analysis

First things first. Voltus and Voltus-Fi are two separate products. They are both…

• 3 min read
Voltus-Fi , AMS , electromigration , custom , analog , Voltus , Virtuoso , analog mixed signal , IR drop , power , Breakfast Bytes , EMIR

SoC and IP

50 Gbps Ethernet is on the Way

Here is my report from the most recent IEEE 802.3 standards meeting, which was held…

• 2 min read
Ethernet standards , Automotive Ethernet , IEEE 802.3 , Ethernet , Marris , 50G Ethernet

Verification

Cheating Tetris

Remember Tetris? We’ve all played it at some point in our lives. You know, the game…

• 2 min read
Verification Computing Platform , Palladium , Tetris , Emulation

Breakfast Bytes

The Design that Made ARM

I sat down with Simon Segars, the CEO of ARM last Friday. As I said yesterday , it…

• 4 min read
Simon Segars , ARM7TDMI , ARM , Breakfast Bytes

Breakfast Bytes

Happy 25th Birthday, ARM

This week is ARM's 25th anniversary. It is actually on Friday, the 27th, but since…

• 7 min read
ARM processor , Simon Segars , VSLI , ARM

Verification

A Coverage Time-Saving Tip

How often has this happened to you? You are re-using a part of a previous design…

• 2 min read
IMC , coverage , Incisive Enterprise Simulator , Incisive , metric-driven verification , MDV , Incisive Enterprise Simulator (IES)

Breakfast Bytes

Marie Pistilli Passed Away

Marie Pistilli, who was injured in a car-crash in October (as I included in my first…

• less than a min read

Breakfast Bytes

The CDMA Story and Qualcomm

When second generation cell-phone technology, GSM, was developed the biggest issue…

• 4 min read
wireless , GSM , cdma , Qualcomm

Breakfast Bytes

Technology Transfer: The Stanford/Berkeley Model

At SEMICON West this year, I attended an interesting presentation by Steven Forrest…

• 4 min read
marc andreessen , two cultures , Stanford , technology transfer , Berkeley , steven forrest , a16z , mosaic , andreeson , a16z podcast , cp snow

System, PCB, & Package Design 

What's Good About Allegro PCB Designer Manufacturing Option? It's NEW in the 16.6…

Wow! There is an extremely powerful option available for PCB designers in the 16…

• 2 min read
PCB Layout and routing , manufacturing option , Allegro 16.6 , 16.6 , SPB , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

Breakfast Bytes

How to Do Body Bias with GLOBALFOUNDRIES 22FDX and Innovus Implementation System

Last week Cadence put out a press release that the Cadence implementation flow had…

• 5 min read
ARM Techcon , 22fdx , body bias , implementation , GlobalFoundries , ARM

Whiteboard Wednesdays

Whiteboard Wednesdays—Basic Principles of Deep Learning

In this week's Whiteboard Wednesdays video, Chris Rowen discusses the basic principles…

• less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , deep learning , Tensilica , data analysis , data extraction , pattern recognition
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