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SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
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Blog - Post List

Latest blogs

SoC and IP

HoloLens Is at the Tip of the Tensilica Iceberg, With Processors That Scale to Any…

Microsoft provided details of their HoloLens HPU at HotChips this week, revealing…

• less than a min read
IP , controller , Tensilica , augmented reality

Breakfast Bytes

Piloted Driving: Audi's View

I hope it isn't a surprise to anyone reading this blog that the share of a vehicle…

• 3 min read
Automotive , Audi , automotive electronics , imec , itf brussels , itf

Breakfast Bytes

A Raven Has Landed: RISC-V and Chisel

In Game of Thrones, ravens are George RR Martin's way of getting information around…

• 4 min read
risc-v , riscv , chisel , raven , UC Berkeley , Breakfast Bytes

Academic Network

ISVLSI 2016: Advanced-Node Custom Layout Symposium Keynote

I had an exciting week in July here in Pittsburgh, PA with the IEEE Computer Society…

• 2 min read
ISVLSI , VLSI , Cadence Academic Network , academia , Virtuoso , advanced node layout

Breakfast Bytes

Provisioning Devices Securely

Asaf Ashkenazi of Cryptography Research (now part of Rambus) talked about provisioning…

• 3 min read
provisioning , security , cryptography research , IoT , wearables , linley mobile , Internet of Things , Breakfast Bytes

Breakfast Bytes

Who Put the Silicon in Silicon Valley?

I think the person who has the strongest claim to putting the silicon in Silicon…

• 5 min read
marc andreessen , William Shockley , Silicon Valley , Breakfast Bytes

Computational Fluid Dynamics

Ford: Multidisciplinary Design Optimization of a Turbocharger Compressor

Ford chooses Fidelity Optimization to increase the performance of turbocharger compressors…

• 4 min read
CFD , Automotive , automotive engineering , turbomachinery , Computational Fluid Dynamics , fluid dynamics , Fidelity CFD , CFD Applications , Turbo

Breakfast Bytes

What’s for Breakfast? Preview August 29th to September 2nd (video)

https://youtu.be/X-hVSQfbtFE

• less than a min read
self-heading , Apple , risc-v , Audi , CDNLive , autonomous driving , MIPI , isa , cdnlive boston , Soundwire , aging , FinFET , ADAS , piloted driving , Krste Asanović , instruction set architecture

Verification

Coverage Maximization

Searching for “automatic coverage maximization” results with ~16 million hits. Alas…

• 4 min read
Specman , coverage , Functional Verification , Testbench simulation , Coverage-Driven Verification , CDV , e , e language , Funcional Verification , team specman , specman elite , verification

Breakfast Bytes

Wearables: Growing at 38% CAGR?

At what has now become the Linley Mobile and Wearables Conference, Linley pointed…

• 3 min read
smartwatch , quaqlcomm , Linley , wearables , smart watch , mobile

SoC and IP

MIPI DevCon 2016 – Mobile and Beyond

MIPI DevCon 2016 – Mobile and Beyond The word “beyond” may bring up thoughts of…

• 6 min read
MIPI Alliance , ADAS

Whiteboard Wednesdays

Whiteboard Wednesdays - Radar Signal Processing Optimized for the Tensilica Fusion…

In this week's Whiteboard Wednesday video, Pushkar Patwardhan discusses the advantages…

• less than a min read
Whiteboard Wednesdays , IP , radar signal processing , Tensilica

Breakfast Bytes

CDNLive India Keynote

The keynote at CDNLive Bengaluru was given by Michal Siwiński. Since day 1 of CDNLive…

• 2 min read
CDNLive India , SDE , system design enablement , Breakfast Bytes

SoC and IP

Less is More With MIPI I3C

There is little doubt that Internet of Things has become the next big thing in business…

• 1 min read
peripherals , IoT , MIPI , i2c , sensors , hdr , I3C , sensewire , hub

Breakfast Bytes

SEMICON Best of the West: Coventor

SEMICON West runs a sort of award program called Best of the West. Companies submit…

• 3 min read
semicon west , semi , Coventor , semulator3d , best of the west

Breakfast Bytes

Perspec Modeling

The post A Perspective on Perspec earlier this week introduced the idea of Perspec…

• 3 min read
Perspec , perspec system verifier , UML , system verilog

Analog/Custom Design

High-Sigma Showdown: Which Method is Better?

The adoption and usage of advanced node technology (16nm and below) has been extraordinary…

• 3 min read
variation tsmc hsmc sss sampling high sigma

Breakfast Bytes

What's for Breakfast? August 22nd

http://youtu.be/ZkZQAW6Gl7M Monday: At SEMICON West the winner of the "Best of…

• less than a min read
provisioning , security , Intel , CDNLive India , linley group , shockley , wearables , Qualcomm , Fairchild , a16z , cdnlive bengaluru , Coventor , mobile , Silicon Valley

Breakfast Bytes

Palladium and Protium Platforms, the Hardware Twins

The Palladium Z1 is an enterprise-level emulation system. If you don't already know…

• 4 min read
palladium z1 , Protium , Palladium , Emulation , FPGA prototyping
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