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SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
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Blog - Post List

Latest blogs

Breakfast Bytes

Omnia Simulation in Tres Partes Divisa Est

"Omnia Gallia in tres partes divisa est" were the opening words to Julius Caesar…

• 3 min read
verilog-xl , Verilog , rocketick , rocketsim , simulation

Whiteboard Wednesdays

Whiteboard Wednesdays - Tensilica Fusion G3 DSP Features and Benefits

In this week's Whiteboard Wednesdays video, Paul Garden provides more details on…

• less than a min read
Whiteboard Wednesdays , IP , Tensilica , Tensilica Fusion G3

Verification

10 New Protocols to Design and Integrate Your SoC in Record Time

This month we released 10 new Verification IP for leading-edge protocols! Did I say…

• 1 min read
SPI NAND , Verification IP , VIP , MIPI , DisplayPort , USB , DSI , octal spi , Ethernet , Tensilica , design , Type-C , and Verification IP , USB UFS

Breakfast Bytes

A Perspective on Perspec System Verifier

Today we have UVM, the universal verification methodology. This is great for verifying…

• 4 min read
Perspec , perspec system verifier , cache coherency , ARM , power

SoC and IP

Building the Cars of the Future

The big buzz in the automotive industry lately is autonomous driving vehicles. Companies…

• 3 min read
Verification IP , VIP , Automotive Ethernet , CAN , automotive electronics , Ethernet , Design IP and Verification IP , Lin

Breakfast Bytes

What's for Breakfast? August 15th

It's verification week this week, with 5 posts about various aspects of Cadence's…

• 1 min read
Breakfast Bytes

Breakfast Bytes

Verification Technology Update

At CDNLive in Bengaluru last week, Michal Siwiński gave a technology update on verification…

• 4 min read
Perspec , Protium , VIP , Palladium , Incisive , Indago , JasperGold , Breakfast Bytes , vManager , verification

Breakfast Bytes

5G, Coming Soon to a Phone Near You

At the Linley Mobile Conference recently, the morning after Linley's keynote was…

• 3 min read
5G , Linley , simultaneous connectivity , mobile , Breakfast Bytes

Verification

The Evolution of MIPI DSI

The MIPI DSI specification has come a long way from the days of its early introduction…

• 2 min read
Verification IP , MIPI Alliance , IoT , VIP , MIPI , DSI , Tensilica , design , Internet of Things , and Verification IP

Breakfast Bytes

CDNLive Bengaluru: Day 2

CDNLive Bengaluru takes place over two days. But it is organized very differently…

• 7 min read
NXP , CDNLive India , CDNLive , whats for breakfast , cdnlive bengaluru , implementation , tapeout

Breakfast Bytes

CDNLive Bengaluru: Day 1

As I did at the Design Automation Conference in Austin earlier this year, I will…

• 7 min read
CDNLive , bengaluru , bangalore , Breakfast Bytes , analog devices

Whiteboard Wednesdays

Whiteboard Wednesdays—Radar Signal Processing for Automotive Applications

In this week's Whiteboard Wednesdays video, the first of a two-part series, Pushkar…

• less than a min read
Automotive , DSP , Whiteboard Wednesdays , IP , radar , Tensilica

Breakfast Bytes

CDNLive Bengaluru, a Long Journey

I've not been to Bengaluru for about 20 years, when I ran engineering at Compass…

• 3 min read
CDNLive India , bengaluru , Cadence India , Breakfast Bytes

System, PCB, & Package Design 

Five Industry Experts Coming to CDNLive Boston to Discuss Signal and Power Integrity…

Who Are They? Istvan Novak – Senior Principal Engineer at Oracle Kevin Roselle…

• less than a min read
CDNLive , Signal Intregrity , Power Integrity , Boston , PCB design

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Persistent Snap and Select? New Capabilities…

The 16.6-2015 Allegro PCB Editor release introduces a few new features that provide…

• 2 min read
PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor

Breakfast Bytes

What's for Breakfast? August 8th

This is the first weekly video "What's for Breakfast?" that previews the blog entries…

• 1 min read
risc-v , CDNLive India , CDNLive , preview , whats for breakfast? , cdnlive bengaluru , mobilemobile 5g , Breakfast Bytes

Breakfast Bytes

Breakfast Bytes Guide to Japan Travel

Cadence was shut down for the week of July 4th, so I went to Japan with a friend…

• 5 min read
tsukiji , kyoto , osaka , tourism , narita , kansai , japan , travel , haneda

Breakfast Bytes

Merger Mania

At the recent GSA Silicon Summit at the Computer History Museum in Mountain View…

• 6 min read
Wally Rhines , merger mania , gsa silicon summit , mergers , gsa , Breakfast Bytes , acquisitions , Mentor

Breakfast Bytes

Chipworks Looks at Smartphones

Chipworks buys hundreds of devices every year and strips them down to look at the…

• 4 min read
Intel , Apple , Samsung , TSMC , Linley , wearables , mobile , GlobalFoundries , smartphones , Breakfast Bytes
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