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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays - A Peek Inside Future Automotive Networks

In this week's Whiteboard Wednesdays video, Charles Qi explains future automotive…

• less than a min read
Whiteboard Wednesdays , automotive engineering , Automotive Ethernet , automotive electronics , automotive IP

Life at Cadence

Cadence Celebrates Women’s Day in India

Cadence India celebrated Women’s Day across all four sites on March 9th. Women’s…

• less than a min read
Insights on Culture , inclusion , Women's Day , HeforShe , Cadence India

Whiteboard Wednesdays

Whiteboard Wednesdays - Why a DSP is the Right Choice for Imaging and Vision Alg…

In this week's Whiteboard Wednesday's video, the third in a three-part series, Pulin…

• less than a min read
DSP , Whiteboard Wednesdays , IP , vision algorithms , Tensilica , imaging algorithms

Verification

Incisive vManager Free Video Training

The Incisive vManager tool for professional verification planning and management…

• 2 min read
Functional Verification , Cadence Online Support , Incisive , training , vManager

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Replace Padstack? 16.6 Has Several New Enhancements…

The Allegro PCB Editor 16.6 ‘ Replace Padstack ’ command is now available as a context…

• less than a min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro 16.6 , Routing , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

System, PCB, & Package Design 

Generate Daisy Chain Patterns for Test Vehicles and Other Applications Using the…

With increasing design complexity comes the need to create test vehicles to qualify…

• 5 min read
Co-Design , 16.6 , manufacturing , early adopter , SiP Layout , substrate design tools , Physical layout and co-design , daisy chain

Whiteboard Wednesdays

Whiteboard Wednesdays—DSP for Automotive Applications

In this week's Whiteboard Wednesday's video, Charles Qi discusses how Cadence scaleable…

• less than a min read
Automotive , DSP , Whiteboard Wednesdays , IP , Tensilica

Verification

Accelerating the Next Big Shift in Verification

Today Cadence announced that we are aligning our proposal to the Accellera Portable…

• 5 min read
pswg , scenario , UML , software-driven verification , Accellera

Whiteboard Wednesdays

Whiteboard Wednesdays - Addressing SoundWire Design Challenges

In this week's Whiteboard Wednesdays video, the second in a two-part series, Charles…

• less than a min read
Design IP , Whiteboard Wednesdays , software design challenges , MIPI SoundWire

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Line Width Retention? 16.6 Has It!

Currently, user line width overrides are permitted during the Add Connect command…

• 1 min read
PCB Layout and routing , 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro

System, PCB, & Package Design 

Integrate PVS into Your IC Package Design Flow to Optimize for Manufacturability…

As package substrates continue to get more complex, often resembling silicon as much…

• 4 min read
IC Packaging and SiP Design , GDSII , DRC , stream , 16.6 , SPB , PVS

SoC and IP

USB Type-C Ecosystem, Issues, and Opportunities

USB Type-C is an innovation that is transforming the electronics industry. What is…

• less than a min read
USB Type-C , DisplayPort , MCCI , Alternate Mode

Whiteboard Wednesdays

Whiteboard Wednesdays—The Applications and Benefits of 802.11ad

In this week's Whiteboard Wednesdays video, Bob Salem provides a detailed overview…

• less than a min read
wireless , Whiteboard Wednesdays , 802.11x , 802.11ad

Digital Design

Five-Minute Tutorial: Innovus Clock Tree Synthesis and Debugger

Hi Everyone, Last time, our Five-Minute Tutorial focused on the new Innovus Placement…

• less than a min read
training , ccopt , clock tree synthesis , debugger , Digital Implementation , Innovus

SoC and IP

Cadence IP for USB Works over Type-C (Proof Inside)

There is no other specification in the history of USB that caused so much discussion…

• 1 min read
USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Whiteboard Wednesdays

Whiteboard Wednesdays - Evolution of Automotive Electronics

In this week's Whiteboard Wednesdays, Charles Qi talks about the evolution of electronics…

• less than a min read
Whiteboard Wednesdays , IP , functional safety , infotainment , automotive electronics , Tensilica , ADAS

System, PCB, & Package Design 

What's Good About Allegro PCB Editor NC Route? 16.6 has Several New Enhancements…

There are a few NC Route enhancements in the 16.6 Allegro PCB Editor release. Read…

• 1 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , Routing , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays—Managed NAND Flash Devices

In this week's Whiteboard Wednesdays video, Lou Ternullo provides a detailed overview…

• less than a min read
Whiteboard Wednesdays , IP , NAND flash , system design

SoC and IP

Electrical Validation of DDR4 Interfaces

Developing SoCs with high-speed memory interfaces, such as DDR4, presents substantial…

• 1 min read
Design IP , DDR4 , LPDDR , DDR , Sigrity , Tektronix
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