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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Verification

Securing Invisible Things … or “Why Denial Works!”

The opening keynote of the Embedded World conference in Germany left me with chills…

• 4 min read
security , Automotive , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , Vulnerabilities , cadence , Acceleration , Functional Verification , Safety , McClure , System Design and Verification , System Development Suite , Driver Assist , embedded software , Palladium XP , Emulation , DVcon , Testing , Cylance , ADAS , ARM , Error Injection , Embedded World , Schirrmeister , Hacking Exposed , verification

System, PCB, & Package Design 

What's Good About Allegro AMS New Advanced Options? They’re in the 16.6 Release!

The Allegro AMS Simulator (analog/mixed-signal) 16.6 release adds several enhancements…

• 2 min read
AMS , Allegro 16.6 , advanced options , AMS simulator , 16.6 , MS simulation , Allegro AMS , PSPICE , SPB , PCB design , Grzenia , analog/mixed signal

Analog/Custom Design

"Smart Devices" and How They Affect Your Mixed-Signal SOC Verification

We are seeing a huge trend -- the mobile revolution is changing the way we go about…

• 4 min read
AMS , DVCon 2013 , CDNLive 2013 , SV-DC , Verilog-AMS , analog , Incisive , Mixed-Signal , smart devices , analog behavioral models , analog/mixed-signal , Virtuoso , Internet of Things , RNM , Verilog AMS , mixed signal , SenseAware , wreal , Virtuoso environment , Schematic Model Generator , mixed-signal verification

Verification

Application Specific System-Design and Verification at Embedded World and DVCon

This week (February 25th 2013) is a busy one for system development and the Cadence…

• 3 min read
Nuremberg , virtual platforms , applications , virtual prototypes , System Design and Verification , application-specific , Mobile World Congress , System Development Suite , embedded software , automotive electronics , Internet of Things , software , DVcon , apps , software development , hardware/software , embedded systems , Embedded World , Schirrmeister

Verification

Embedded World 2013: Virtual Platforms Connected to Everything

Sometimes it is hard to explain why certain ideas take off and why others don’t.…

• 3 min read
virtual prototyping , RPP , Virtual System Platform , virtual platforms , embedded world conference , embedded software , VSP , Palladium XP , Emulation , system design , Rapid Prototyping Platform , System Design & Verification , Embedded World , linux , simulation

Digital Design

Five-Minute Tutorial: Create Encounter Power System (EPS) Power-Grid Views For Standard…

In today's tutorial, I'm giving you a sample EPS (Encounter Power System) script…

• 4 min read
power-grid views , Low Power , rail analysis , current density , LEF , EPS , standard cells , Digital Implementation , qrc , Power Analysis , signoff , EM , IR drop , five minute tutorial , encounter power system , power

Verification

What the 787 Dreamliner Can Teach Us About SoC design

The commercial aircraft industry is at a stage where it innovates at a much slower…

• 6 min read
Dreamliner , Boeing , Apple , 787 Dreamliner , TLM , fire , 787 , C-to-Silcon , Harvard Business Review , SoC , IP assembly , system design , SoC design , Apple A6 , SystemC , outsourcing , iPhone , Jay-Z , System Design and Verification

Verification

Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial Feb…

TUTORIAL : Fast Track Your UVM Debug Productivity with Simulation and Acceleration…

• 1 min read
SystemVerilog , Specman/e , AVS , metric driven verification (MDV) , debug , Functional Verification , Debug Performance , debug tutorial , Incisive Debug Analyzer , Mixed Signal Verification , DVcon , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , IES-XL

System, PCB, & Package Design 

What's Good About OrCAD Capture’s Signal Integrity Flow? The Secret's in the 16.6…

With the 16.6 release, you now have the capability of utilizing the PCB SI tools…

• 1 min read
PCB SI , capture , Constraint-driven PCB Design flow , constraint databases , Allegro 16.6 , Design Entry CIS , Signal Intregrity , 16.6 routing , electrical constraints , IBIS , SigXP UI , OrCAD Capture , 16.6 , PCB Signal and power integrity , Capture CIS , Capture-CIS , High Speed , Constraint Manager , Layout , Signal Integrity , OrCAD , OrCAD PCB SI , PCB Signal integrity , Allegro PCB SI , Constraints , Grzenia , SI analysis and modeling , PCB Capture , Schematic , Allegro

Analog/Custom Design

Virtuosity: 10 Things I Learned In January By Browsing Cadence Online Support

This month's highlighted content includes helpful information on wreal modeling,…

• 2 min read
Virtuoso Space-based Router , Rapid Adoption Kit , encounter , calibration , Virtuoso , Analog Design Environment , ADE-XL , AMS simulation , mixed signal , interoperability , wreal , Custom IC Design

Verification

Why C-to-Silicon Compiler HLS has Supported IEEE 1666-2011 SystemC All Along

Recently one of our competitors issued a press release claiming to be the first high…

• 1 min read
asynchronous reset , IEEE 1666-2011 , Incisive , SystemC , C-to-Silicon Compiler , QoR

Verification

IBM and Cadence Collaboration Improves Verification Productivity

Technology leaders like IBM continuously seek opportunities to improve productivity…

• 2 min read
SystemVerilog , uvm , collaboration , IEEE 1800 , Metric Driven Verification , IBM , simvision , OVM , Tom Cole , Incisive , Mixed-Signal , Acellera VIP TSC , MDV , IEV , IES , vManager , IFV , IES-XL

Analog/Custom Design

Things You Didn't Know About Virtuoso: Drag and Drop

I love it when I'm sitting in a meeting with my colleagues or with a group of customers…

• 2 min read
Analog Design Environment , ViVa-XL , Virtuoso IC6.1.5 , IC 6.1 , VIrtuoso drag and drop , IC 6.1.5 , ADE , Virtuoso , ViVA , ADE-XL , drag and drop , Custom IC Design

System, PCB, & Package Design 

What's Good About ADW’s Configuration Manager? Look to 16.6 and See!

The 16.6 Allegro Design Workbench (ADW) Configuration Manager has been enhanced!…

• 1 min read
Allegro 16.6 , 16.6 , Allegro Design Workbench , Library flow , Library and design data management , SPB , design data management , design , PCB design , Grzenia , Librarians , library

System, PCB, & Package Design 

Allegro Sigrity Makes its Debut at DesignCon 2013

After Cadence acquired Sigrity in July 2012, we heard many of the same questions…

• 2 min read
PCB , SI , PI , IC Packaging , SiP Design , Griffin , Designcon 2013 , Power Integrity , Signal Integrity , EDACafe , Sigrity , Allegro PCB Editor , SI analysis and modeling , Allegro Sigrity

Digital Design

Quick Reference - 8 Ways to Optimize Power Using Encounter Digital Implementation…

Everyone knows that the increasing speed and complexity of today's designs implies…

• 4 min read
EDI , EDI system , Vt partition , low power tips , leakage , Jaiswal , EDI 11.1 , 8 ways , encounter digital implementation system , Encounter Digital Implementation , optLeakagePower , Leakage Optimization , power optimization , EDI 11 , dynamic power

Verification

Using the ‘restore -append_logs' Feature

As described in Specman Advanced Option appnote , Specman Elite supports dynamic…

• 3 min read
AF , Specman , debug , Functional Verification , restore append , reseeding , log files , e language , specman elite , restore , restore-append_logs , SAO , dynamic load , simulation

Verification

DVCon 2013 for Formal and ABV Users

At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects…

• 3 min read
Incisive Formal Verifier , Joe Hupcey III , ABV , Joerg Mueller , metric driven verification (MDV) , Functional Verification , Formal Analysis , NVIDIA , ABVIP , formal , formal apps , Vigyan Singhal , Incisive , Incisive Enterprise Verifier , Mike Stellfox , Chris Komar , Oski Technology , DVcon , assertions , formal scoreboard , MDV , IEV , Oski , Formal verification , IFV , Assertion-based verification

Verification

DVCon 2013 for the Specmaniac

At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects…

• 3 min read
Specman , Specman/e , methodology , verification strategy , metric driven verification (MDV) , debug , Functional Verification , Formal Analysis , formal , Incisive Debug Analyzer , e , e language , Mike Stellfox , DVcon , Aspect Oriented Programming , simulation , AOP , verification
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