Cadence Blogs

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team 27 Aug 2025 • 1 min read

IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate 21 Aug 2025 • 4 min read

news story , featured , Cadence Academic Network

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera 31 Jul 2025 • 2 min read

featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team 23 Jul 2025 • 2 min read

featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso

cdns - all_blogs_categories

All 6036
Corporate News 191
Life at Cadence 199
Academic Network 166
Analog/Custom Design 760
Artificial Intelligence 23
Cloud 16
Computational Fluid Dynamics 358
Data Center 39
Digital Design 422
Learning and Support 55
RF Engineering 113
SoC and IP 406
System, PCB, & Package Design 982
Verification 1283
Cadence Japan 3

CFD（数値流体力学) 45
中文技术专区 14
カスタムIC／ミックスシグナル 188
PCB、IC封装：设计与仿真分析 136
PCB解析／ICパッケージ解析 44
PCB設計／ICパッケージ設計 61
RF /マイクロ波設計 44
Spotlight Taiwan 61
The India Circuit 88
定制IC芯片设计 79
データセンター 7

Whiteboard Wednesdays 253

Blog - Post List

Latest blogs

28 nm IC Design: The Devil Is In The Details

Smaller process technologies are enticing chip makers with bigger rewards from their…

Nora 14 Mar 2011 • 4 min read

EDI , lithography , CMP , Litho , 28nm , DRC , metal thickness , LVS , Advanced Node , NanoRoute , encounter , via rules , LPE , digital , Silicon Realization , Digital Implementation , interconnect rules , Variation , stress , parasitics

Virtuoso IC6.1.5: Software and Fine Red Wine

Software, like fine red wine, can get better with age as well -- but it requires…

NewYorkSteve 14 Mar 2011 • 7 min read

AMS , parasitic-aware design , Low Power , Virtuoso IC6.1.5 , custom/analog , Analog Simulation , analog , Constraint-driven , IC 6.1.5 , Mixed-Signal , Virtuoso , mixed signal , Custom IC Design , DFM , parasitics

A Modest Proposal: Using Formal to Close Coverage Gaps

In my last blog post , I summarized some of our activities at DVCon and mentioned…

tomacadence 11 Mar 2011 • 4 min read

NextOp , coverage , Functional Verification , Formal Analysis , formal , BugScope , Breker , DVcon , assertion synthesis , assertions , Closure , metrics , CVC , Formal verification

DATE Spotlights System Development University Investment in Europe

In this guest blog Markus Winterholer, R&D engineer at Cadence, explains why he's…

Steve Brown 10 Mar 2011 • 2 min read

university , DATE , Winterholer , UML , Daedalus , University Booth , VOCIS , System Design and Verification

RF Engineering

Tips for Simulating a Transmit Mixer in SpectreRF

Some typical questions that I receive from newer SpectreRF users are: How do I simulate…

Tawna 10 Mar 2011 • 8 min read

RF , RF Simulation , Spectre RF , ADE-L , Analog Simulation , MMSIM , spectreRF , Spectre , RF design , harmonic balance , mixer

Encounter Puzzler #3 Solution: Renaming a Net Logically

Once again, the Encounter Digital Implementation designer community has stepped up…

BobD 9 Mar 2011 • 4 min read

conformal , dbGet , net renaming , encounter , Digital Implementation , Encounter Digital Implementation , puzzler , tcl

System, PCB, & Package Design

What's Good About ADW’s Flow Manager? Check Out the ADW16.3 Release and See!

The ADW16.3 Allegro Design Workbench has a desktop cockpit that allows engineers…

Jerry GenPart 9 Mar 2011 • 4 min read

PCB , SPB16.3 , Allegro Design Entry , part developer , DEHDL , mechanical parts , Directive Lockhing , Allegro 16.3 , SPB 16.3 , High Speed , Allegro Design Workbench , Library flow , SPB , LRM , PCB Editor , Design Entry HDL , design data management , design , Library Revision Manager , "PCB design" , PCB design , Design Entry , ADW 16.3 , Allegro PCB Editor , Librarians , ConceptHDL , library , ADW , Schematic

Video: Optimizing Area and Power Using Formal Methods

At DVCon 2011, a paper presented by Freescale and Cadence described a truly novel…

TeamVerify 8 Mar 2011 • 1 min read

Low Power , ABV , methodology , Formal Analysis , formal , Freescale , Incisive , Chris Komar , DVcon , IFV

Video: New Cadence Verification IP Catalog (With Denali Inside!)

Clearly UVM 1.0 was the main story at DVCon last week, but there was other big news…

jvh3 8 Mar 2011 • less than a min read

uvm , Functional Verification , ABVIP , Cadence VIP portfolio , OVM , VIP , EDA360 , Verification IP modeling , DVcon , eRM

TLM 2.0, UVM 1.0 and Functional Verification

The DVCon 2011 conference was held this week and the Accellera Universal Verification…

Sharon 7 Mar 2011 • 8 min read

SystemVerilog , uvm , TLM , Functional Verification , OVM , TLM 2.0 , ports , DVcon , Accellera , SystemC , Accellera VIP TSC , VMM , verification

DVCon? Are You Sure It's Not UVMCon or MSVCon?

As I write this, I've just returned from the most important conference and tradeshow…

tomacadence 4 Mar 2011 • 2 min read

uvm , Functional Verification , MSV , EDA360 , Mixed-Signal , random test , DVcon , Accellera , mixed signal , verification

System, PCB, & Package Design

What's Good About Cadence Online Support Product Pages? – Check Out This List!

I wrote about the new Cadence Online Support features in one of my blog posts last…

Jerry GenPart 2 Mar 2011 • 2 min read

PCB SI , PCB , SCM , PCB Layout and routing , SI , SPB16.3 , Allegro Design Entry , AMS , SiP , PCB PI , IC Packaging , Design Entry CIS , social networking , Signal Intregrity , DEHDL , FPGA-PCB Co-Design , Digital SiP design , specctra , SigXP UI , FPGA System Planner , OrCAD Capture , Allegro 16.3 , Capture CIS , Capture-CIS , High Speed , APD , Support , Smoke Analysis , SigWave , SPB , webinar , SPB16.2 , PCB Editor , Constraint Manager , Design Entry HDL , ASA , Layout , design , FSP , OrCAD , PCB Signal integrity , PCB design , Design Entry , windows 7 , Allegro PCB Editor , Librarians , SI analysis and modeling , ConceptHDL , SPB16.01 , OrCAD PCB Editor , GRE , Online Support , library , ADW , PCB Capture , Schematic , FPGA , Allegro

Specman Application Note: Improving Verification Productivity With Dynamic Load and…

Are you looking for new approaches to improve your verification productivity by 40…

teamspecman 1 Mar 2011 • 3 min read

IntelliGen , Specman , metric driven verification (MDV) , Functional Verification , vPlan , simvision , EDA , Incisive , e language , team specman , specman elite , Aspect Oriented Programming , testbench , Incisive Enterprise Simulator (IES) , AOP , IES-XL

Encounter Puzzler #3: Renaming a Net Logically

The other day a designer E-mailed me: How can we rename a net in Encounter? I followed…

BobD 28 Feb 2011 • 1 min read

dbGet , Encounter Digital Implementation , puzzler , tcl

Do You Have a DATE with Software? Cadence Does!

How important is the software market to Cadence and as an element of the EDA360 vision…

Steve Brown 28 Feb 2011 • 3 min read

DATE , IP , IP-XACT , debug , RTL , System Design and Verification , SoC , virtual prototype , software , Virtual Platforms

At DVCon 2011 Next Week

Next week my colleagues and I will be at DVCon 2011 in force, ready to regale you…

jvh3 25 Feb 2011 • 2 min read

Industry Insights , ABV , TLM , Functional Verification , formal , OSCI , OVM , EDA360 , Coverage-Driven Verification , EDA , Mixed Signal Verification , Incisive , Mixed-Signal , DVcon , OOP , multi-language , SystemC , Formal verification , techtorial , AOP

Cadence Investment in SystemC Continues -- NASCUG SystemC Day at DVCon

Don't lose touch with what's new in the world of SystemC! Cadence is a long time…

Steve Brown 24 Feb 2011 • 2 min read

virtual platforms , virtual prototypes , System Design and Verification , OSCI , DVcon , Accellera , Jim Hogan , IEEE P1666 , SystemC , NASCUG , SystemC Day

Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Si…

Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a…

PeteMc 23 Feb 2011 • 2 min read

dynamic rail analysis , Static timing analysis , ets , EDI system , Signoff Analysis , DRC , design rules , LVS , SI analysis , EPS , noise analysis , EDI 10.1 , Virtuoso , Digital Implementation , In-Design Signoff , Timing analysis , Power Analysis , signoff , tapeout , IR drop , Digital end-to-end flow , EM Failures , timing convergence , DFM