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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Blog - Post List
Latest blogs

SoC and IP

Does Samsung really scare Japan? EETimes’ Junko Yoshida thinks so.

EETimes' Junko Yoshida just published an article titled “5 reasons why Samsung scares…

• 1 min read

SoC and IP

Marc Greenberg’s “big resistor” model of semiconductor DRAM power consumption

Too many DRAM choices. If you want low power DRAM, do you choose LPDDR1, LPDDR2,…

• 2 min read

SoC and IP

OCZ Enyo USB 3.0 SSD reviewed by PC Perspective video

Earlier, we covered the announcement of OCZ’s Enyo USB 3.0 external SSD. Now PC Perspective…

• less than a min read

SoC and IP

InfoWeek video series chronicles storage and SSD Evolution. Part 1 runs 8 minutes…

Can you spare nine minutes to get a really good grounding in SSD concepts? No? How…

• 1 min read

System, PCB, & Package Design 

What's Good About Browsing For Power Pins in Capture? It's In SPB16.3!

The SPB16.3 release of Allegro Design Entry CIS (Capture) now allows you to browse…

• 1 min read
"capture CIS" , Capture CIS' , Design Entry CIS , OrCAD Capture , SPB 16.3 , Capture CIS , Capture-CIS , OrCAD , Design Entry , Schematic

SoC and IP

Squeeze bandwidth inefficiencies out of DDR DRAMs in memory subsystem designs

This blog starts with a simple, sad truth: DDR DRAMs are naturally inefficient. If…

• 6 min read

Digital Design

Mixed Signal: Why The Sudden Attention?

With DAC 2010 rapidly approaching, we can again expect that lots of EDA and IP vendors…

• 2 min read
DAC , SoC , Mixed-Signal , Digital Implementation , mixed signal

SoC and IP

Why is it so difficult to interface with DRAMs?

One of the maxims in the world of system design is that it has always been relatively…

• 3 min read

Verification

The Future of OVM, VMM, and UVM

In my last blog , I took a look back at the history of how we got to the first delivery…

• 3 min read
SystemVerilog , uvm , methodology , Functional Verification , Open Verification Methodology , OVM , VIP , Accellera , Accellera VIP TSC , VMM

SoC and IP

Google TV and Intel’s CE4100 SOC (Sodaville)--is this a world-beating combo or what…

Having vacuumed up most of the world’s very large and growing Internet advertising…

• 5 min read

SoC and IP

MemCon 2010, July 28: Time to Register. Hundreds already have!

How’s your July shaping up? No, that’s not just an idle question about your future…

• 1 min read

Verification

Tech TIP: Incisive Formal GUI Updates - Making It Easier

The Incisive Formal GUI has had some recent changes made to it. You asked for the…

• less than a min read
ABV , Functional Verification , Formal Analysis , formal , Incisive , IEV , IFV

SoC and IP

Seagate Tweet unleashes avalanche of speculation: fast gamers' 2.5-inch HDD with…

Earlier this week, Seagate sent out the following Tweet: “Your hard drive is…

• 1 min read

System, PCB, & Package Design 

Favorite Features Of An IC Package Designer: Rich And Diverse Set Of Import And Export…

This is the second in a series of discussions we would like to open up regarding…

• 1 min read
SPB16.3 , SiP , Analog and RF SiP design , Digital SiP design , 3D-IC , Allegro 16.3 , IC Packaging and SiP , IC Packaging & SiP design , SPB , wirebond profile library , IC Package Physical layout and co-design , Kulicke & Soffa

SoC and IP

LPDDR2: The new mainstream memory for embedded and mobile applications?

Yesterday, ST-Ericsson announced a new smartphone platform called the U8500 which…

• 3 min read

RF Engineering

New Time-Saving Feature in IC6.1.4 ISR2: Plot S-Parameter Data Directly From ViVA…

If you haven't heard about it....there is a new feature in IC6.1.4 ISR2 which makes…

• 2 min read
RFIC , Virtuoso Spectre , Spectre RF , ADE-L , RF designer , MMSIM , Spectre , ViVA , RF design , Circuit Design , harmonic balance , pss

System, PCB, & Package Design 

What's Good About ADW Part Lifecycle? Numerous Improvements in the SPB16.3 Release

The SPB16.3 release of Allegro Design Workbench (ADW) now adds several new key features…

• 1 min read
Allegro Design Workbench , Library flow , Library and design data management , PCB design , ADW 16.3 , Librarians , ADW

SoC and IP

Party on at DAC, says Denali

Back by popular demand, the Denali DAC party. The big one. With the bells and whistles…

• 1 min read

RF Engineering

Using RF Simulation Technology for Analog Applications

The particular nature of analog circuits puts restrictive requirements on circuit…

• 1 min read
RF Simulation , Analog Simulation , RF design , Analog Smart
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