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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Verification

Tech Tip: Weighting Generation of "Extreme" Values

[ Team Specman welcomes guest blogger Vitaly Lagoon, an Architect in the Generation…

• 1 min read
IntelliGen , Specman , Verification methodology , Functional Verification , Incisive , e , team specman , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

Verification

Heads-up: DVClub Boston Coming Up On June 1

Back on March 19 here in Silicon Valley, verification guru Brian Bailey gave a great…

• less than a min read
events , verification strategy , Functional Verification , DVClub

SoC and IP

Memory Company Financials, 1Q09

1Q09 Better than 4Q08, but still terrible: Memory makers continued to suffer…

• 8 min read

Analog/Custom Design

Things You Didn't Know About Virtuoso: Tabs and Bookmarks

Do you remember the first time you used a browser with tabs? All of a sudden, there…

• 2 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

Way Worse Than The Real Thing

This week Cadence and Virtutech announced a collaborative effort to bring together…

• 2 min read
cdnlive! emea 2009 , System Design and Verification , Incisive Enterprise Simulator , embedded software , Incisive , Coverage Driven Verification for Embedded Software , embedded SW engineer , ISX , Hardware/software co-verification , ESL , architect , Virtutech , Coverage Driven Verification

System, PCB, & Package Design 

Innovative Approach to Optimized FPGA Pin Assignment

Cadence has been a leader in silicon-package and package-board co-design for over…

• less than a min read
FPGA-PCB Co-Design , PCB design , FPGA

Verification

ESL Verification News From CDNLive! EMEA

Hello from CDNLive! EMEA in Munich. Another year has passed, and it’s time…

• less than a min read
System Design and Verification , Incisive Enterprise Simulator , Incisive , SystemC analysis , System simulation and analysis , Coverage Driven Verification for Embedded Software , SystemC , Incisive Software Extensions , Hardware/software co-verification , debugging , ESL , Virtutech , Coverage Driven Verification

Verification

System D&V at CDNLive! EMEA

CDNLive! EMEA has started today. I arrived here (Munich Germany) from SFO paying…

• 1 min read
System Design and Verification , Palladium , xtreme , Virtutech

Verification

5 min Demo: e Coding With AMIQs DVT IDE

For those of you who can't make it to the CDNLive Munich Designer Expo this week…

• less than a min read
IEEE 1647 , eclipse , Specman , CDNLive , Functional Verification , e , team specman , specman elite , AMIQ

Digital Design

Getting Started with dbSet

A while back, I posted a blog called Getting Started with dbGet . It was a brief…

• 2 min read
dbGet , dbSet , encounter , Digital Implementation

Verification

SystemC Debug: A Summary of Summary Probes

SystemC goes well beyond generic C and C++ to provide a number of semantic constructs…

• 5 min read
Verification planning and management , TLM , System Design and Verification , System simulation and analysis , debugging , ESL , verification

Analog/Custom Design

Don't Confuse Primary With Only

Given the small nature of the EDA industry, I have read with some interest company…

• 1 min read
mixed-signal simulators , CDNLive , Primary , analog , Sanyo , Cusstom IC Design

Verification

e Shareware on OVMWorld.org and Cadence Community Sites

As our loyal readers know, we on Team Specman works hard to include code examples…

• 1 min read
IEEE 1647 , Specman , Functional Verification , OVM e , vr_ad , e , team specman , OVMWorld , verification

System, PCB, & Package Design 

What's Good About New Smoke Analysis Devices? Check out the SPB16.2 Release and See

The AMS Simulator Smoke Analysis has been enhanced in the SPB16.2 release to support…

• 2 min read
SPB 16.2 , AMS simulator , Smoke Analysis , PCB design , model editor

Verification

ISX Presentations at CDNLive! Munich

As we head into next weeks CDNLive! event in Munich it's great to see today's post…

• 1 min read
cdnlive! emea 2009 , System Design and Verification , ISX

SoC and IP

Taiwan: From Death by DRAMs to Finding Foundry Success

Vanguard International Semiconductor, Once a DRAM failure, is Now a Successful Junior…

• 7 min read

SoC and IP

Taiwan DRAM Makers...Trapped by Their Culture?

Can Taiwanese DRAM Makers Decide What to do Next...in Time? We recently saw…

• 3 min read

Analog/Custom Design

Things You Didn't Know About Virtuoso: Introduction

A while ago, I somehow ended up on the mailing list of a rather odd catalog called…

• 3 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

IEEE P1647-2010 Call For Participation

Attention Specmaniacs: the IEEE 1647 working group is looking for a few additional…

• 2 min read
IEEE 1647 , Specman , Functional Verification' signal integrity , OVM e , e , OVM-e , eRM , AOP
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