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SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI
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Blog - Post List

Latest blogs

Verification

App Note Spotlight: Choosing the Incremental Elaboration Flow That’s Right For Y…

Welcome to another App Note Spotlight! One of the biggest issues facing verification…

• 2 min read
incremental elaboration , Flows , Functional Verification , MSIE

Breakfast Bytes

Spectre with a Red Hat, part 2

This is the second post about Red Hat's John Masters presentation at FOSDEM 2018…

• 6 min read
red hat , Spectre , jon masters , linux

Breakfast Bytes

Spectre with a Red Hat

A couple of weekends ago it was FOSDEM 2018, the largest conference on open source…

• 8 min read
security , meltdown , Redhat , Spectre , linux

The India Circuit

Incubators, Accelerators and Fabless Chip Design at IESA Vision Summit 2018

This week we had one of the Indian semiconductor industry’s biggest and most well…

• 6 min read
Vision Summit , Government of Karnataka , fabless chip , IESA , India Electronics and Semiconductor Association , Priyank Kharge , semiconductor incubator

Breakfast Bytes

Engineers, and How to Manage Them

I've covered various aspects of an EDA company: sales, marketing, application engineers…

• 6 min read
management , ambit , engineering

Breakfast Bytes

What the FEC is Forward Error Correction?

What is forward error correction (FEC)? It is automatically correcting errors in…

• 8 min read
fec , hamming , galois , Breakfast Bytes , shannon , forward error correction , networking , ECC

Breakfast Bytes

What's For Breakfast? Video Preview March 5th to March 9th 2018

https://youtu.be/YesJPmKCeio Coming from Embedded World, Nuremberg (camera Robert…

• less than a min read
AMD , IBM , 3nm , red hat , imec , Spectre , Embedded World , linux

Whiteboard Wednesdays

Whiteboard Wednesdays - Unpacking the DFI Low-Power Interface

In this week's Whiteboard Wednesday, John MacLaren describes the operation of the…

• less than a min read
Low Power , Whiteboard Wednesdays , DFI , DDR PHY

Breakfast Bytes

Embedded World 2018: Dreaming of Electric Cars

I am at embedded world in Nuremberg. One thing that is not here is warm weather.…

• 7 min read

SoC and IP

Why Software-Based GPS Is Great for Location-Based IoT Applications

At the Cadence booth at Mobile World Congress in Barcelona, we’re featuring a demo…

• 1 min read

Breakfast Bytes

How Many Journalists per Square Acre?

It doesn't matter how low your standard is for science journalism, the journalists…

• 5 min read
kilowatt , degree , kilowatt hour

Analog/Custom Design

Take Advantage of Advancements in Real Number Modeling and Simulation

Verification is the top challenge in mixed-signal design. Bringing analog and digital…

• 2 min read
real number modeling , analog , Mixed-Signal , RNM , mixed-signal verification

Verification

Xcelium and Cavium: What’s the Deal?

So—you may have heard that Xcelium Parallel Simulator is available on Arm servers…

• 1 min read
thunder x2 , video , Cavium , xcelium

Breakfast Bytes

Patents: Licensed by the Ton

I wrote recently about What Happens in a Patent Lawsuit? Today, I want to look at…

• 8 min read
patent , troll , non-practising entity , cross-licensing , npe

SoC and IP

Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP

What is a software GPS, what does it have to do with Tensilica DSP IP, and why would…

• 4 min read
Galileo , GPS , IoT , Tensilica DSPs

Breakfast Bytes

How Do You Get to Be CEO?

I wrote last week about Being CEO and I said that I'd done it twice in my career…

• 6 min read
board , management , chief executive officer , leadership , CEO

Analog/Custom Design

Virtuosity: New Eye Diagram Measurements

The Eye Diagram assistant in Virtuoso Visualization and Analysis allows you to create…

• 2 min read
Eye Mask , Analog Design Environment , ViVa-XL , ADE Explorer , Explorer , ADE XL , ADE , eye diagram , Analog Design Environment , ViVA , ADE-XL , Virtuosity , Custom IC Design , ADE Assembler

Verification

New AMBA 5 ACE/AXI Specification: More About Atomic Transactions

As discussed in the previous installment of this blog, a new class of atomic transactions…

• 1 min read
amba5 , ACE5 , AXI5 , Atomic Transactions

Breakfast Bytes

What's For Breakfast? Video Preview February 26th to March 2nd 2018

https://youtu.be/wq86edcqTdw Coming from Building 10 lobby (camera Sean) Monday…

• less than a min read
fec , patent , journalism , Embedded World , forward error correction
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