Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Digital Design

Transitioning Your LEF-Based EDI System Design Flow to OpenAccess

The trend of combining analog and digital circuits on a single chip has been growing…

• 4 min read
EDI system , LEF , Cadence Online Support , Mixed-Signal , encounter , Virtuoso , oa , Digital Implementation , PDK , mixed signal , LEF to OpenAccess , Brian Wallace , OpenAccess , blog

RF Engineering

MMSIM12.1 SpectreRF Preview of Coming Attractions! - Part 1

Greetings! MMSIM 12.1 contains many new features to aid RF designers. Here's a preview…

• 2 min read
RF , RF Simulation , analog/RF , envelope , Circuit simulation , Wilsey , shooting newton , Virtuoso Spectre , HB , Spectre RF , spectre spectreRF , ADE-L , Analog Simulation , MMSIM , fast envelope , analog , ADE , RF spectre spectreRF , spectreRF , Spectre , RF design , harmonic balance

Verification

Function Level C Interface – New C Interface for Specman

Working with the conventional Specman C language interface has two major disadvantages…

• 2 min read
AF , Specman , function level , Functional Verification , C Interface , e language , Specman C , TCM , PLI

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Component Alignment? See for Yourself in 16

The Component Alignment feature is available in Placement Edit Application mode.…

• 1 min read
PCB , DFA , Allegro 16.6 , 16.6 , Placement Edit , Component Alignment , PCB Editor , PCB design , Grzenia , Spacing , Allegro PCB Editor , alignment , Allegro

Verification

Creating Custom File Systems and the Linux Loop Device

A few weeks ago we had a crisis at our house. My son managed to delete the data from…

• 7 min read
virtual platforms , Linux loop , File System , virtual prototypes , chroot , System Design and Verification , embedded software , Ubuntu , linaro , custom file systems , mount -o loop , ARM Architecture , Zynq virtual platform , linux , Jason Andrews , Zynq-7000 , simulation

Verification

How Many Cycles are Needed to Verify ARM’s big.LITTLE on Palladium XP?

At the recent CDNLive! India user conference, Deepak Venkatesan and Murtaza Johar…

• 5 min read
ESL Market , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , cadence , Acceleration , Functional Verification , System Design and Verification , big.LITTLE , System Development Suite , embedded software , Palladium XP , Emulation , ARM , cost of ownership

System, PCB, & Package Design 

What's Good About the SPB 16.6 Release? Exciting Features To Improve Design Productivity

The SPB 16.6 Release is available! You can download it from the Cadence Software…

• 4 min read

Analog/Custom Design

Recent Events Show That Customer Interest in Mixed-Signal Remains High

The well attended Mixed-Signal Technology Summit last month really demonstrated the…

• 2 min read
ARM Techcon , ARM Cortex M0 , mixed signal design , Technology on tour , MS ToT , mixed-signal ToT , mixed-signal methodology , mixed signal methodology , tech on tour , mixed signal solution , Open Access , Cortex-M , Mixed-Signal , Mixed-Signal Technology Summit , analog/mixed-signal , mixed-signal book , Cortex-M0 , Mixed-Signal Tech Summit , mixed signal methodology guide , mixed signal , OA: OpenAccess , cortex M , mixed-signal design , ARM , Mixed-Signal Methodology Book , tech-on-tour , OpenAccess , AMS Verification

Verification

Event Report: Club Formal San Jose – Features and Techniques for Experts, Verification…

Last week over 35 power users from over a dozen companies came together for the latest…

• 5 min read
Incisive Formal Verifier , ABV , Team Verify , Functional Verification , Formal Analysis , formal apps , Vigyan Singhal , Incisive , Incisive Enterprise Verifier , Chelsio , Chris Komar , apps , assertions , Club Formal , bypass logic verification , IEV , Oski , Formal verification , IFV , liveness , Assertion-based verification

Verification

Ubuntu 12.10 on a Virtual Platform at ARM Techcon

Next week (Oct. 30-Nov. 1) ARM TechCon 2012 is at the Santa Clara Convention Center…

• 1 min read
ARM Techcon , Virtual System Platform , virtual platforms , programmer's guide , virtual prototypes , Cortex-A9 , Cortex-A , VSP , Ubuntu , ARM , Quantal Quetzal , Ubuntu 12.10 , linux , Jason Andrews , Zynq-7000

Verification

Margins are Costly - Don't Let Them Grow Out of Control!

Last week, Professor Jan Rabaey of the University of California at Berkeley gave…

• 2 min read
High-Level Synthesis , Low Power , Rabaey , low power summit , margins , rtl compiler , variability , C-to-Silicon Compiler , HLS

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Stipple Highlighting? See for Yourself in 16

The 16.5 Allegro PCB Editor now has the added ability to accentuate objects and layers…

• 1 min read
PCB , PCB Layout and routing , application mode , Allegro GUI , stipple highlighting , super filter , Allegro 16.5 , PCB Editor , Layout , "PCB design" , PCB design , Grzenia , SPB16.5 , Allegro PCB Editor , stipple , Allegro

Analog/Custom Design

Press Release About TSMC Flow, Blog from ARM Validate Cadence’s Mixed-Signal and…

A press release and a blog post caught my attention this week (October 15, 2012)…

• 2 min read
AMS , EDI , ets , uvm , microcontrollers , ARM Cortex M0 , Mixed-Signal On Top , MS ToT , cadence , AMS Designer , TSMC , EPS , Mixed-Signal , Virtuoso , mixed signal methodology guide , mixed signal , PVS , ARM , encounter power system , Encounter Timing System , IUS

System, PCB, & Package Design 

What's Good About ADW’s Multiple Shopping Lists? Check out the 16.5 Release and See

The 16.5 Allegro Design Workbench (ADW) now supports multiple shopping lists. In…

• less than a min read
PCB , shopping lists , data management , flow manager , Library flow , multiple shopping lists , Allegro 16.5 , Library and design data management , component browser , design data management , PCB design , Design Entry , Grzenia , SPB16.5 , Librarians , library , Allegro

Analog/Custom Design

SKILL for the Skilled: Part 4, Many Ways to Sum a List

In the previous posts SKILL for the Skilled: Many Ways to Sum a List (Parts 1, 2…

• 5 min read
Team SKILL , Virtuoso IC6.1.5 , Jim Newton , sum a list , SKILL for the Skilled , recursion , Virtuoso , Lisp , SKILL++

Verification

Changing the Game with Processor Based Emulation

I have always been fascinated by game changing moves. Some are more successful than…

• 7 min read
RPP , FPGA Based Prototyping , prototyping , cadence , Acceleration , debug , Functional Verification , System Design and Verification , Palladium , System Development Suite , embedded software , Emulation , Software Development and Debug , Rents Rule , Schirrmeister , system integration , FPGA

Digital Design

Five-Minute Tutorial: Why You Should Be Running Early DRC

Everyone knows you have to run signoff DRC before you tape out a design. Sometimes…

• 3 min read
EDI , IP , routing access , filler , power grid , DRC , early DRC , endcap , encounter digital implementation system , NanoRoute , welltap , Verify Geometry , metal fill , signoff , macros , memories

Verification

UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Every SoC project uses multiple languages. Even if the design itself is purely Verilog…

• 1 min read
IEEE 1647 , SystemVerilog , uvm , IEEE 1800 , UVM-ML , Functional Verification , OVM , e , webinar , UVM ML , multi-language , Accellera , SystemC , multi-language UVM , IES , IES-XL

Verification

Recorded Webinar: Using Metric-Driven Verification and Formal Together For Higher…

[Preface: the upcoming " Club Formal " on October 17 here at the Cadence San Jose…

• 3 min read
coverage , Functional Verification , Metric Driven Verification , Formal Analysis , formal , Incisive , webinar , Incisive Enterprise Verifier , Chris Komar , enriched metrics , MDV , IEV , debugging , John Brennan , simulation , Formal verification , IFV
CDNS - Fix Layout Hompage