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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

BoardSurfers: Footprint Creation Using a STEP Model in Library Creator

Read how you can easily create accurate footprints from a vendor-provided STEP Model…

• 3 min read
Library Creator , PCB Editor , 17.4-2019 , ECAD-MCAD Library Creator , PCB design , Allegro

Breakfast Bytes

Memorial Day: Conway and Collatz

Do you know what the Collatz Conjecture is? John Horton Conway died recently, as…

• 6 min read
offtopic

Breakfast Bytes

It's the Second Mouse That Gets the Cheese

I love short phrases that make you think, "Wait...what?" and then you think about…

• 7 min read
late to market , moat , early to market , barriers to entry , startup

System, PCB, & Package Design 

IC Packagers: Determining Minimum Spacing Values in a Design

I don’t remember the first time I was asked this question. At its core, the question…

• 4 min read
Allegro Package Designer

Breakfast Bytes

A History of Neural Networks

Research on biological neurons started back in the 1940s, before computers, and long…

• 8 min read
featured , neural networks , AI , neural nets

Verification

Interconnect Beyond PCIe: CXL and Cache Coherent Interconnect

As the de facto IO interconnect technology, PCIe has commendably addressed the performance…

• 2 min read
Verification IP , VIP , PCIe , Internet of Things , Denali , PCI Express , verification

Academic Network

Learning in a Virtual World

The Cadence Academic Network enables you to access Cadence tools remotely, and, in…

• 3 min read
Europractice , Cadence Academic Network , remote learning , CMC Microsystems , online learning

Analog/Custom Design

Virtuosity: Rewind and Replay the Top 10 Cadence Virtuosity and Virtuoso Video Diary…

With new content being posted nearly every week under Custom IC Design Blogs, there…

• 3 min read
Analog Design Environment , Cadence blogs , ICADVM18.1 , ADE Explorer , Virtuoso Space-based Router , MODGEN , Auto Place and Route , System Design Platform , APR , Layout , Virtuoso , Virtuosity , Virtuoso Layout Suite , Custom IC , simulation , IC6.1.8 , ADE Assembler , MTS

定制IC芯片设计

Virtuoso Meets Maxwell：Virtuoso射频解决方案——流程一体化的技术改革

我刚刚从马萨诸塞州的波士顿，这个极具革命盛名的地方回到家，在那我参加了2019国际微波大会（IMS 2019）。今年峰会很精彩，不仅因为波士顿风景迷人，更因为这里是…

• less than a min read
Chinese blog , Cadence blogs , ICADVM18.1 , VRF , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Layout EXL , virtuoso system design platform , Virtuoso , Allegro

Breakfast Bytes

Which Passwords Should You Change?

I was talking to someone who consults to Cadence on various aspects of security.…

• 9 min read
security , tfa , password , two-factor authentication

Breakfast Bytes

Sunday Brunch Video for 17th May 2020

https://youtu.be/We9eDDOn-Cg Made in "Instanbul" (camera Carey Guo) Monday: Why…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

极致PCB设计全流程 I 技巧三：规则管理器应用技巧

本期技巧篇内容与大家分享规则管理器（Allegro® Constraint Manager，简称CM）中输入数据的几个细节操作以及“信号不允许表层布线”的规则设置…

• less than a min read
设计经验 , Chinese blog , 软件技巧 , training , webinar , PCB设计 , 中文 , 直播网课 , online training , Allegro , 专家培训

PCB、IC封装：设计与仿真分析

极致PCB设计全流程 I 基础三：有效进行规则设置

规则驱动设计理念：通过正确抽象、完整设置的规则，为PCB设计质量保驾护航。 设计过程中，保证设计者的行为正确是至关重要的，如果规则出现问题，那么过程执行得再好都无济于事…

• 1 min read
Chinese blog , 经验分享 , training , webinar , PCB设计 , 中文 , 直播网课 , online training , Allegro , 专家培训

Life at Cadence

My Life at Cadence Video Series: Sneharsi Nag

Cadence recently interviewed five of our amazing women engineers for a new video…

• less than a min read
Insights on Culture , inclusion , Culture , STEM , cadence , my life at cadence , women , engineering

Digital Design

SSV 20.1 Base Release Now Available

The SSV 20.1 production release is now available for download.

• 3 min read
Vector Profiler , Signoff ECO , Tempus , Tempus PI , integrated signoff , Power Integrity , Voltus , Voltus-XP

System, PCB, & Package Design 

BoardSurfers: Three Steps to Using Embedded Components

If you think embedding components in a PCB just reduces product size, well that's…

• 4 min read
embedded components , Allegro Package Designer , Allegro PCB Editor

Breakfast Bytes

Tensilica HiFi DSPs with Dolby Atmos for Soundbars

Do you know what a soundbar is? Years ago, if you wanted to build a good home theater…

• 4 min read
HiFi , Tensilica

Digital Design

Library Characterization Tidbits: Reuse to Recharacterize - Improve Productivity…

A write up on how Liberate MX effectively enables you to characterize only the failed…

• 3 min read
memory characterization , incremental run , timing validation , Liberate MX , Digital Implementation , interpolation error , library validation , Rapid Adoption Kits , RAKs

Verification

Catching up with Higher Ethernet Speed: VIP Supports 802.3ck

Draft 1.0 of 802.3ck, also known as 100G per lane, was finally published by IEEE…

• 2 min read
802.3ck , Ethernet VIP , baseR , VIP , 100Gbps , 100G backplane , CGPL
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