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Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
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Blog - Post List
Latest blogs

Verification

Will Software Development Cause Another “Industrial” Revolution?

As you have read here before, Cadence has been working closely with Xilinx to create…

• 3 min read
zynq , edaForum , virtual prototypes , industrial , System-Level Design , Siemens , Virtual Platforms , Industrial Automation , Design Flows , Sanitas

Verification

India Needs Real-World Assertions Too

I've just returned from a week-long trip to India, spending most of my time at the…

• 4 min read
Functional Verification , Old Delhi , Noida , assertions , New Delhi , real-world assertions , India

Verification

Parallel Compilation for SystemC

One of the most common complaints about SystemC is that it takes too long to compile…

• 3 min read
Virtual System Platform , virtual platforms , GNU , parallel compilation , virtual prototypes , embedded software , C , LSF , compile , pallallel compile , make , SystemC , System Design and Verification

System, PCB, & Package Design 

What's Good About ADW’s Configuration Manager? The Secret's in the 16.5 Release!

The Allegro Design Workbench (ADW) Configuration Manager application is designed…

• 1 min read
PCB , data management , Allegro Design Workbench , Library flow , Team design , Allegro 16.5 , design data management , configuration manager , design , PCB design , SPB16.5 , Librarians , library , ADW , Allegro

Verification

Event Report: Club Formal Shanghai

The first "Club Formal" event in China was held in Shanghai on Oct. 21 2011, and…

• 2 min read
events , Verification IP , China , ABV , verification strategy , Functional Verification , ABVIP , formal , ADS , assertions , Club Formal , IEV , Assertion-Driven Simulation , Shanghai , Formal verification , IFV , Jin Tang , Assertion-based verification

Analog/Custom Design

SKILL for the Skilled: Introduction to Classes -- Part 4

In several previous postings we introduced the problem of solving the sudoku puzzle…

• 6 min read
Team SKILL , programming , Sudoku , object orientation , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL

Verification

Report on CDNLive! India 2011: Provocative Keynotes, Detailed Papers, and Robots…

Recently I had the honor of presenting the functional verification roadmap at CDNLive…

• 2 min read
Suman Ray , Low Power , Joe Hupcey III , ABV , Apurva Kalia , verification strategy , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Manu Chopra , Incisive , Lokesh Pundreeka , SVA , Lego , assertions , robot , MDV , Rubik's Cube , Formal verification , IFV , Assertion-based verification

System, PCB, & Package Design 

What's Good About Refresh, Copy Project, TCL in SCM? 16.5 Has a Few New Enhancements

There are several enhancements in the 16.5 System Connectivity Manager ( SCM ) /…

• less than a min read
PCB , SCM , Allegro Design Entry , Constraint-driven PCB Design flow , refresh option , Allegro 16.5 , ASA , Allegro System Architect (ASA) , Front-end PCB design , Design Entry , SPB16.5 , copy project , Schematic , Allegro , tcl

Verification

Shameless Promotion: Free Club Formal San Jose, Formal Scoreboard Webinar

Please join Team Verify and other D&V engineers for one or both of the following…

• 1 min read
scoreboard , ABV , methodology , verification strategy , Joerg Mueller , Functional Verification , Formal Analysis , formal , EDA360 , webinar , Club Formal , IEV , Formal verification , IFV , Assertion-based verification

Digital Design

CDNLive! Silicon Valley 2012 Abstracts Due November 11th, 2011

The Call for Papers for CDNLive! Silicon Valley 2012 is open now through Friday November…

• 1 min read
CDNLive , cadence , encounter , Cadence users , Digital Implementation , CDNLive!

Analog/Custom Design

Fred Discovers 1000x-10000x Speedup Using wreal Models

This is the second installment in an ongoing series of blog posts that includes an…

• 1 min read
real value , Verilog-AMS , analog , Mixed-Signal , analog behavoral , Verilog , Virtuoso , Fred , mixed signal , wreal , SPICE

RF Engineering

Guidelines for Maximizing Speed vs Accuracy for Harmonic Balance - Part 2

I am often asked for guidelines on maximizing speed vs. accuracy for SpectreRF…

• 3 min read
RF , RF Simulation , analog/RF , HB , Spectre RF , ADE-L , MMSIM , Virtuoso Spectre Simulator GXL , RF spectre spectreRF , Virtuoso Spectre Simulator XL , spectreRF , RF design , harmonic balance

System, PCB, & Package Design 

What's Good About Single Mode Operation in DEHDL? The Secret's in the 16.5 Release

Due to architectural changes in SPB16.5 Design Entry HDL (DEHDL), we no longer require…

• 12 min read
PCB , Allegro Design Entry , DEHDL , Allegro 16.5 , Design Entry HDL , Front-end PCB design , design , PCB design , Design Entry , SPB16.5 , ConceptHDL , PCB Capture , Schematic , Allegro , single mode operation

Analog/Custom Design

How Fred Discovered Mixed-Signal Behavioral Modeling

Introduction This is the first of a series of blogs where we will add pieces to the…

• 3 min read
AMS , mixed signal design , AMS-Designer , Verilog-AMS , analog , Mixed-Signal , Virtuoso , Fred , assertions , mixed signal , wreal

Analog/Custom Design

A Moment to Mourn -- John McCarthy, Father of Lisp

Here lies a Lisper Uninterned from this mortal package Yet not gc'd While we…

• 1 min read
John McCarthy , McCarthy , software development , Lisp , Custom IC Design , SKILL

Verification

Welcome to the Zynq-7000 Virtual Platform

As you might guess we are pretty excited about the Virtual Platform development for…

• 4 min read
zynq , virtual platforms , TLM , EPP , Zynq-7000' , virtual prototypes , Cortex-A9 , System Design and Verification , software , SystemC , xilinx , ARM , linux , extensible , FPGA

Verification

Verification and the Need for Collaboration

Earlier this week I was at the ARM TechCon in Santa Clara, a show that gets better…

• 2 min read
NextOp , ARM Techcon , uvm , collaboration , Zocalo , Functional Verification , Standards , partnerships , VA , EDA360 , EDA , Duolog , verification alliance , UCIS , AMIQ

Verification

Report: Formal Analysis Papers at CDNLive India 2011

On October 19, 2011 in Bangalore, India more than 800 engineers across all domains…

• 3 min read
ABV , CDNLive , Functional Verification , Formal Analysis , ABVIP , formal , Lokesh Pundreeka , ADS , metric-driven verification , assertions , MDV , IEV , Assertion-Driven Simulation , Formal verification , IFV , India , Assertion-based verification

System, PCB, & Package Design 

What's Good About PCB SI IOCell Editor in Model Editor? 16.5 Has a Few New Enhancements

There are currently multiple options for model editing in the Allegro PCB SI environment…

• 2 min read
PCB SI , PCB , SI , I/O , SiP , Signal Intregrity , Digital SiP design , SigXP UI , PCB Signal and power integrity , High Speed , Allegro 16.5 , SigWave , Signal Integrity , Allegro PCB SI , PCB design , SPB16.5 , IOCell Editor , SI analysis and modeling , model editor , library , Allegro
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