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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

Analog/Custom Design

Virtuosity: Do I Need To Run a Simulation To Plot From a Text File?

You'll be glad to hear the answer is No! In Virtuoso Visualization and Analysis,…

• 2 min read
Analog Design Environment , ViVa-XL , ADE Explorer , Explorer , Analog Simulation , ADE XL , ADE , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , ViVA , Virtuosity , Assembler , ADE Assembler

Breakfast Bytes

embedded world: Mark Papermaster of AMD

The opening keynote from embedded world in Nuremberg was by Mark Papermaster, who…

• 4 min read
epyc , Automotive , ryzen , AMD , Embedded World

Breakfast Bytes

3nm Cadence and imec

I started Breakfast Bytes on October 8, 2015, my first day back at Cadence. The very…

• 4 min read
Genus , testchip , 3nm , imec , Innovus , 5nm

Whiteboard Wednesdays

Whiteboard Wednesdays - Error Correction Code Implementations in Memory Controller…

In this week's Whiteboard Wednesdays video, Jing Liu provides a simple explanation…

• less than a min read
DDR Controller , Whiteboard Wednesdays , ECC

Verification

App Note Spotlight: Choosing the Incremental Elaboration Flow That’s Right For Y…

Welcome to another App Note Spotlight! One of the biggest issues facing verification…

• 2 min read
incremental elaboration , Flows , Functional Verification , MSIE

Breakfast Bytes

Spectre with a Red Hat, part 2

This is the second post about Red Hat's John Masters presentation at FOSDEM 2018…

• 6 min read
red hat , Spectre , jon masters , linux

Breakfast Bytes

Spectre with a Red Hat

A couple of weekends ago it was FOSDEM 2018, the largest conference on open source…

• 8 min read
security , meltdown , Redhat , Spectre , linux

The India Circuit

Incubators, Accelerators and Fabless Chip Design at IESA Vision Summit 2018

This week we had one of the Indian semiconductor industry’s biggest and most well…

• 6 min read
Vision Summit , Government of Karnataka , fabless chip , IESA , India Electronics and Semiconductor Association , Priyank Kharge , semiconductor incubator

Breakfast Bytes

Engineers, and How to Manage Them

I've covered various aspects of an EDA company: sales, marketing, application engineers…

• 6 min read
management , ambit , engineering

Breakfast Bytes

What the FEC is Forward Error Correction?

What is forward error correction (FEC)? It is automatically correcting errors in…

• 8 min read
fec , hamming , galois , Breakfast Bytes , shannon , forward error correction , networking , ECC

Breakfast Bytes

What's For Breakfast? Video Preview March 5th to March 9th 2018

https://youtu.be/YesJPmKCeio Coming from Embedded World, Nuremberg (camera Robert…

• less than a min read
AMD , IBM , 3nm , red hat , imec , Spectre , Embedded World , linux

Whiteboard Wednesdays

Whiteboard Wednesdays - Unpacking the DFI Low-Power Interface

In this week's Whiteboard Wednesday, John MacLaren describes the operation of the…

• less than a min read
Low Power , Whiteboard Wednesdays , DFI , DDR PHY

Breakfast Bytes

Embedded World 2018: Dreaming of Electric Cars

I am at embedded world in Nuremberg. One thing that is not here is warm weather.…

• 7 min read

SoC and IP

Why Software-Based GPS Is Great for Location-Based IoT Applications

At the Cadence booth at Mobile World Congress in Barcelona, we’re featuring a demo…

• 1 min read

Breakfast Bytes

How Many Journalists per Square Acre?

It doesn't matter how low your standard is for science journalism, the journalists…

• 5 min read
kilowatt , degree , kilowatt hour

Analog/Custom Design

Take Advantage of Advancements in Real Number Modeling and Simulation

Verification is the top challenge in mixed-signal design. Bringing analog and digital…

• 2 min read
real number modeling , analog , Mixed-Signal , RNM , mixed-signal verification

Verification

Xcelium and Cavium: What’s the Deal?

So—you may have heard that Xcelium Parallel Simulator is available on Arm servers…

• 1 min read
thunder x2 , video , Cavium , xcelium

Breakfast Bytes

Patents: Licensed by the Ton

I wrote recently about What Happens in a Patent Lawsuit? Today, I want to look at…

• 8 min read
patent , troll , non-practising entity , cross-licensing , npe

SoC and IP

Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP

What is a software GPS, what does it have to do with Tensilica DSP IP, and why would…

• 4 min read
Galileo , GPS , IoT , Tensilica DSPs
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