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Featured

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 27 Aug 2025 • 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
Corporate 21 Aug 2025 • 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
Vinod Khera 31 Jul 2025 • 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 23 Jul 2025 • 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Breakfast Bytes

Neural Networks and the Future

The Panel Session The recent embedded neural network symposium held at Cadence…

Paul McLellan 17 Feb 2017 • 8 min read
deep learning , enns , neural networks , autonomous vehicles , debugging

Breakfast Bytes

Chris Rowen: Neural Networks—The New Moore's Law

In addition to being the master of ceremonies for the recent embedded neural network…

Paul McLellan 16 Feb 2017 • 3 min read

Breakfast Bytes

Kunle Olukotun: Scaling Machine Learning Performance

The keynote at the recent Embedded Neural Network Symposium held recently at Cadence…

Paul McLellan 15 Feb 2017 • 5 min read
buckwild! , Delite , plasticine , hogwild! , neural networks

Whiteboard Wednesdays

Whiteboard Wednesdays - Coherent Interconnect Verification Challenges

In this week's Whiteboard Wednesdays video, Nimrod Reiss discusses the challenges…

References4U 14 Feb 2017 • less than a min read
Verification IP , Whiteboard Wednesdays , throughput , VIP , latency , snoop filtering , Nimrod Reiss , interconnect verification

Breakfast Bytes

Jeff Bier: When Every Device Can See

Jeff Bier is the founder of the Embedded Vision Alliance, which runs the annual Embedded…

Paul McLellan 14 Feb 2017 • 3 min read
deep neural network , deep learning , Embedded Vision Alliance , machine learning , neural network , machine vision

Academic Network

EDA Workshop in Taiwan

Cadence Academic Network recently participated in the 2016 IEEE and CEDA Workshop…

Tracy Zhu 13 Feb 2017 • 1 min read
academic workshop , academia

Breakfast Bytes

What's For Breakfast? Video Preview February 20th to 24th 2017

https://youtu.be/EVZ4T8TPim8 Coming from inside a Microsoft Hololens Monday…

Paul McLellan 13 Feb 2017 • less than a min read
holoens , DesignCon , spie advanced lithography , Mobile World Congress , MWC , rocketsim , target impedance , parallel simulation

Analog/Custom Design

Virtuoso Video Diary: Eye Masks

Have you ever plotted an eye diagram in Virtuoso Visualization and Analysis XL and…

TeamADE 13 Feb 2017 • 4 min read
Eye Mask , Analog Design Environment , Eye , ADE GXL , ViVa-XL , ADE Explorer , Analog Simulation , ADE XL , ADE , Virtuoso Analog Design Environment , ADE-GXL , Analog Design Environment , ViVA , ADE-XL , Virtuoso Video Diary

Breakfast Bytes

The Second Embedded Neural Network Symposium

A couple of weeks ago, Cadence held the second embedded neural network symposium…

Paul McLellan 13 Feb 2017 • 8 min read
deep neural networks , enns , dnn , embedded neural networks , neural networks

Breakfast Bytes

Integrated Bus Routing Solution

For most chips, the automatic routing in Innovus—NanoRoute—works well. But there…

Paul McLellan 10 Feb 2017 • 3 min read
integrated bus routing solution , grid-based routing , analog , Innovus , high frequency router

Breakfast Bytes

Circuits and Systems for Security and Privacy

One of the perks of writing this blog is that I get offered review copies of interesting…

Paul McLellan 9 Feb 2017 • 6 min read
security , side channel attacks , encryption , puf , crc press , random number , physically unclonable functions

Breakfast Bytes

Tom Quan on TSMC's Automotive Strategy

Tom Quan recently came to Cadence to talk about TSMC's automotive strategy. Tom and…

Paul McLellan 8 Feb 2017 • 4 min read
Automotive , tom quan , TSMC , 7ff , 16FFC , ISO 26262 , ADAS , 7nm , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview February 13th to 17th 2017

https://youtu.be/HL0GFG9tNP4 Coming from Cadence security camera Monday…

Paul McLellan 7 Feb 2017 • less than a min read
deep learning , machine learning , convolutional neural networks , moore's law , embedded neural networks , neural networks , machine vision

Whiteboard Wednesdays

Whiteboard Wednesdays - Simplify UVM Scoreboarding with Cadence VIP

In this week's Whiteboard Wednesdays video, principal AE Matt Diehl explains how…

References4U 7 Feb 2017 • less than a min read
Verification IP , Whiteboard Wednesdays , VIP , DisplayPort , Matt Diehl

Breakfast Bytes

He Who Goes First Loses, EDA Edition

Yesterday I wrote a post He Who Goes First...Loses about how being first isn't always…

Paul McLellan 7 Feb 2017 • 4 min read
point tools , hunters , EDA , ambit , farmers

Breakfast Bytes

He Who Goes First...Loses

There is a saying, of course, that he who goes first wins. And sometimes, and in…

Paul McLellan 6 Feb 2017 • 5 min read
apple pay , credit cards , m-pesa , tube , london tube

Breakfast Bytes

Handling Variability in the Modern Design Cycle

Igor Keller gave an internal presentation on Handling Variability in the Modern Design…

Paul McLellan 3 Feb 2017 • 6 min read
on chip variation , AOCV , STA , OCV , variability , voltage droop , static timing , layout dependent effects , miller capacitance , SOCV , crosstalk , slew , SSTA

Verification

Preview of an Exciting DVCon

In the overall world of EDA, the Design Automation Conference ( DAC ) is the biggest…

tomacadence 2 Feb 2017 • 3 min read
uvm , prototyping , pswg , Acceleration , Functional Verification , Perspec , System Design and Verification , Palladium , SoC , Emulation , Simulation acceleration , DVcon , Accellera , metric-driven verification , Hardware/software co-verification , portable stimulus , simulation , verification

Breakfast Bytes

What's For Breakfast? Video Preview February 6th to 10th 2017

https://youtu.be/XOS4sfILahc Coming from Design Con 2017 Monday: He Who…

Paul McLellan 2 Feb 2017 • less than a min read
security , Automotive , Routing , TSMC , business strategy , Innovus , privacy
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