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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Breakfast Bytes

It's HOT in Austin in June

Every DAC, Heart of Technology (HOT) organizes an event. This year it will be held…

• 2 min read
dac2016 , DAC , CASEA , HOT , Heart of Technology , Jim Hogan , Breakfast Bytes

Breakfast Bytes

Party Like It's 1999—How the Denali Party Started

As everyone in EDA knows, Denali threw a party at every DAC for what seems like forever…

• 3 min read
dac2016 , DAC , Denali Party , disco inferno , Denali , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—Modular VIP Architecture

In this week's Whiteboard Wednesdays video, Liron Stoler describes how the Cadence…

• less than a min read
Verification IP , Whiteboard Wednesdays , IP , VIP , system-level verification , block-level verification , modular architecture

Breakfast Bytes

CDNLive EMEA: Memories Are Made of This

At CDNLive in Munich, Amjad Qureshi talked about High-Speed DDR and LPDDR Memory…

• 4 min read
LPDDR , CDNLive EMEA , memory IP , DDR , memory interface IP

RF Engineering

Cadence Presenting Four Spectre RF MicroApp Papers at IMS2016, May 22-27

Hello Spectre RF Users, Next week is my all time favorite technical conference -…

• less than a min read
RF , RF Simulation , wireless , analog/RF , HBnoise , Circuit simulation , Wilsey , HB , Spectre RF , pnoise , phase noise , Schaldenbrand , spectreRF , RF design , harmonic balance , pss

Breakfast Bytes

EDPS Cyber Security Workshop: "Anything Beats Attacking the Crypto Directly"

Many of the security breaches that you read about are the results of software failures…

• 5 min read
security , fault injection , side channel attack , Monterey , differential power analysis , EDPS , riscure , cyber security , Breakfast Bytes

Breakfast Bytes

Can You Trust Your IoT Supplier?

A few weeks ago, Nest announced that it was shutting down Revolv. You probably don…

• 4 min read
alphabet , IoT , revolv , tesla , Internet of Things , nest , Breakfast Bytes

Breakfast Bytes

CDNLive EMEA: Do You Know What a FIT Is?

ADAS changes everything about automotive and requires a whole new range of skills…

• 6 min read
functional safety , CDNLive EMEA , automotive design , FIT

Breakfast Bytes

Cadence at DAC: Experts, Presentations, Lunches...and Denali Party Instructions

Cadence is doing a lot at DAC as usual. Here is a summary. But read it carefully…

• 4 min read
dac2016 , DAC , expert bar , Austin , Denali Party , dac53 , Lip-Bu Tan , Denali , 53dc , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—Tensilica Vision P6 DSP Enhanced for CNN

In this week's Whiteboard Wednesdays video, Dennis Crespo discusses the significant…

• less than a min read
DSP , Whiteboard Wednesdays , IP , Vision P6 , Tensilica , convolutional neural networks , CNN

Breakfast Bytes

Bayern München Come to CDNLive EMEA

CDNLive EMEA is nominally held in Munich (München in German) but, in fact, is held…

• 5 min read
Munich , CDNLive , CDNLive EMEA , Breakfast Bytes , Bayern München

System, PCB, & Package Design 

What's Good About the Latest in DEHDL? The 16.6-2015 Release Has Several New Enhancements…

The 16.6-2015 Design Entry HDL (DEHDL) release contains a few new capabilities! Read…

• 1 min read
Cadence Design Systems , hierarchy , Allegro 16.6 , DEHDL , Allegro Design Workbench , hierarchical schematics , SPB , Design Entry HDL , Design Entry , Grzenia , ConceptHDL

Life at Cadence

Cadence Recognized as a Best Workplace for Giving Back

I am so proud of the Cadence team. We were recognized by FORTUNE as #43 on their…

• 1 min read
Insights on Culture , Culture , Community , cadence , giving back , Fortune , GPTW , Tina Jones , Fortune 100 best companies to work for , great place to work

Breakfast Bytes

CDNLive: Design Technology Co-Optimization for N7 and N5

One of the challenges of developing a new node is that there are a lot of moving…

• 2 min read
n5 , Cadence Academic Network , CDNLive , lithography , CDNLive EMEA , imec , n7 , 5nm , 7nm , design of experiments , DTCO

Breakfast Bytes

Corporate Venture Capital for Semiconductor Start-Ups

A couple of weeks ago, Silicon Catalyst organized an evening panel about corporate…

• 5 min read
Intel , Applied Materials , cypress semiconductor , SanDisk , silicon catalyst , Qualcomm , corporate venture capital , wilson sonsini , corporate vc , Breakfast Bytes

Breakfast Bytes

CDNLive: Ericsson Paving the Way for 5G

At CDNLive EMEA in Munich this week, there were two keynotes. The first was by Tom…

• 3 min read
5G , CDNLive EMEA , Ericsson

Breakfast Bytes

DAC: One Month and Counting

It is May already and just a month until DAC. I am sure that you already know that…

• 3 min read
dac2016 , DAC , Austin , dac53 , Design Automation Conference , 53dac

Whiteboard Wednesdays

Whiteboard Wednesdays—New Tensilica Vision P6 DSP

In this week's Whiteboard Wednesdays video, Chris Rowen discusses the new Tensilica…

• less than a min read
DSP , Whiteboard Wednesdays , IP , Chris Rowen , Vision P6 , Tensilica , convolutional neural networks , CNN

Breakfast Bytes

Embedded Vision: The Road Ahead for Neural Networks and Five Likely Surprises

It is the Embedded Vision Summit. Every year this event gets bigger, reflecting the…

• 3 min read
Low Power , Rowen , Embedded Vision Summit , Vision P6 , tensilica vision p6 , Tensilica , convolutional neural nets , high performance , neural nets , Breakfast Bytes
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