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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

High-Level Synthesis—What Expertise Is Needed for Micro-Architecture Tradeoffs?

My most recent blog post mentioned how utilizing new algorithms together with high…

• 5 min read
RAM , micro-architecture , hardware , C-to-Silcon , C , SystemC , HLS , C++

System, PCB, & Package Design 

What's Good About Capture’s NetGroup Update? 16.6 Has a Few New Enhancements!

The 16.6 release of OrCAD Capture provides a few enhancements in the area of NetGroups…

• 1 min read
capture , Cadence Design Systems , Allegro 16.6 , cadence , hierarchical net groups , OrCAD Capture , 16.6 , Capture CIS , Capture-CIS , hierarchical schematics , SPB , design , NetGroups , OrCAD , Grzenia , net groups , NetGroup , Schematic , hierarchical block

System, PCB, & Package Design 

What's Good About FPGA System Planner and Netgroups? 16.6 Has It!

Beginning with the 16.6 SPB release, FPGA System Planner (FSP) can create net groups…

• 2 min read
PCB , Cadence Design Systems , FPGA: ASIC Prototype , Allegro 16.6 , cadence , FPGA-PCB Co-Design , FPGA System Planner , 16.6 , FPGAs , PCB Editor , setup , Layout , Front-end PCB design , design , NetGroups , FSP , PCB design , Constraints , Grzenia , net groups , NetGroup , FPGA , FPGA Pin Assignment , FPGA: PCB

Verification

Accelerated Code and Functional Coverage Using Palladium XP

Code coverage is an effective tool in the verification process—giving insights into…

• 2 min read
IMC , Cadence Online Support , UXE , Palladium XP , Incisive Verification Environment , support.cadence.com , Accelerated SV Covergrooups , Accelerated Coverage , IES

Verification

Coverage Unreachability UNR App - Rapid Adoption Kit

The Cadence Incisive Enterprise Verifier (IEV) team recently developed a self-help…

• 3 min read
coverage , Unreachability , RAK , UNR , IEV , Incisive Enterprise Simulator (IES) , Formal verification

Verification

Generic Dynamic Run-Time Operations with e Reflection, Part 1

Untyped Values and Value Holders The reflection API in e not only allows you to perform…

• 3 min read
AF , Functiional Verification , e language , Funcional Verification , coverage driven verification (CDV) , Aspect Oriented Programming , reflection

Analog/Custom Design

IC6.1.6 Virtuoso Space-Based Mixed-Signal Router (VSR)

Virtuoso Space-Based Router (VSR) is routing solution integrated into the Virtuoso…

• 4 min read
Technology on tour , MS ToT , VSR , mixed-signal ToT , mixed-signal training , Router , tech on tour , Open Access , analog/mixed-signal , OA: OpenAccess , tech-on-tour

System, PCB, & Package Design 

What's Good About DEHDL’s Variant Editor? 16.6 Has Several New Enhancements!

The recent 16.6 QISR-2 for Allegro Design Entry HDL has new capabilities for the…

• 1 min read
Cadence Design Systems , Allegro Design Entry , Allegro 16.6 , cadence , varient editor , 16.6 , SPB , design , Grzenia , ConceptHDL , Schematic , Allegro

System, PCB, & Package Design 

Turn Spreadsheet Ball Maps into Components in Seconds with 16.6 Cadence APD and …

Many designers use ball maps, or spreadsheets wherein each cell corresponds to a…

• 5 min read
IC Packaging and SiP Design , SiP , IC Package , IC Packaging , packaging , spreadsheet , 16.6 , IC Packaging and SiP , IC package design , APD , IC Packaging & SiP design , BGA , Allegro Package Designer , ball maps , Allegro

System, PCB, & Package Design 

What's Good About Allegro PCB Editor ECSets and Ref Des Values? 16.6 Has a Few New…

Beginning with the 16.6 Allegro PCB Editor , the environment variable UPDATE_ECSET_REFDES…

• 1 min read
PCB , Cadence Design Systems , Constraint-driven PCB Design flow , Allegro 16.6 , cadence , electronics design , 16.6 , SPB , PCB Editor , Constraint Manager , design , PCB design , Constraints , Grzenia , Allegro PCB Editor

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Embedded Net Name Display? Check Out 16.6!

A new graphical display option in the 16.6 Allegro PCB Editor embeds net names within…

• 1 min read
PCB , Cadence Design Systems , Allegro GUI , Allegro 16.6 , cadence , Routing , 16.6 , SPB , PCB Editor , PCB routing , Layout , design , vias , "PCB design" , PCB design , Grzenia , pin planning , physical layout design , Allegro PCB Editor , color visibility , stipple , Allegro , etch shapes

System, PCB, & Package Design 

Why Does Signal Integrity Analysis Need to be Power Aware?

Ever since the I/O Buffer Information Specification (IBIS) committee broke away from…

• 2 min read
IBIS Model , High Speed , Signal Integrity , power-aware SI , SI analysis and modeling , Allegro Sigrity

Verification

Starting Virtual Platform Simulation with Cadence Software Developer

Last time, I provided an introduction to the Eclipse setup for the Cadence Virtual…

• 4 min read
eclipse , Virtual System Platform , Embedded Software Debugging , Incisive

Analog/Custom Design

Virtuosity: 16 Things I Learned in September by Browsing Cadence Online Support

Rapid Adoption Kits By now, I think you know what RAKs are, and that they include…

• 3 min read
custom/analog , Routing , Rapid Adoption Kit , pin placement , Virtuoso Analog Design Environment , Layout , Virtuoso , Analog Design Environment , Schematic Editor , ADE-XL , Virtuosity , Custom IC Design , Virtuoso Layout Suite , VLS XL , Virtuoso Layout Suite XL

Analog/Custom Design

SKILL for the Skilled: How to Shuffle a List

The previous post of SKILL for the Skilled presented some ways to systematically…

• 5 min read
Team SKILL , programming , shuffle , Jim Newton , IC615 , SKILL for the Skilled , permutations , random , Lisp , SKILL++ , SKILL

Verification

Combining the Linux Device Tree and Kernel Image for ARM

Back in 2010, I wrote two articles about a SystemC model used to load the Linux kernel…

• 2 min read
Virtual System Platform , virtual platforms , TLM , ARM kernel image , virtual prototypes , VSP , zimage , boot loader , System Design & Verification , SystemC , Linux device tree , ARM , system-level , linux , Jason Andrews , ESL , kernel

Verification

Getting Started with the Cadence Virtual System Platform: Software Developer

Cadence Software Developer is an exciting Eclipse-based product for developing, debugging…

• 4 min read
eclipse , Virtual System Platform

Verification

Trends in Using Software for System Verification

There is a clear trend to use more software running on the CPUs of a design for system…

• 2 min read
Palladium XP , hybrid engines , linux kernel , Virtual Platforms

Verification

e Macro Debugging

When creating a testbench using the MDV methodology, you want to write intelligent…

• 4 min read
AF , Functional Verification , Debug Performance , e macro debugging , e macros , macro debugging , e language , coverage driven verification (CDV) , macros
CDNS - Fix Layout Hompage