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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

Verification

Secrets of the (Verification) Alliance

In a recent post , I discussed the need for cross-vendor cooperation in EDA, especially…

• 3 min read
uvm , collaboration , Specman , Functional Verification , VAalliance , partnerships , VA , VIP , EDA360 , EDA , Verisity , verification alliance , Doulos , AMIQ , Oski , verification

Verification

Video: Meet Incisive Enterprise Verifier R&D Architect Vinaya Singh

Continuing the series of introducing you to the people that create the tools you…

• less than a min read
Joe Hupcey III , ABV , Vinaya Singh , Functional Verification , Formal Analysis , formal , video , assertions , IEV , Assertion-Driven Simulation , Formal verification , Assertion-based verification

System, PCB, & Package Design 

What's Good About Graphical Operation Locking in Capture? You Can Easily Do This…

A schematic page often contains a large number of different types of objects like…

• 8 min read
"capture CIS" , Design Entry CIS , OrCAD Capture , Capture CIS , Capture-CIS , Allegro 16.5 , SPB , design , OrCAD , Design Reuse , Design Entry , SPB16.5 , PCB Capture , Schematic , operation locking

Verification

Update to the OVM Register Package

OVM users have something new to give thanks for this holiday season -- an update…

• 2 min read
uvm , IP-XACT , Functional Verification , OVM , Register Package , Incisive , IES , OVMWorld , verification

Analog/Custom Design

Cadence is the OpenText Connectivity Partner of the Year

Cadence is pleased to be honored by the OpenText Global Partners Program as their…

• less than a min read
ExceedOn Demand , OpenText , Exceed on Demand , remote access , analog , connectivity partner , Open Text , Virtuoso , Custom IC Design

Verification

Video: Meet Formal and ABV R&D Team Leader Deepak Pant

Inspired by the positive response to my interview of Formal R&D Distinguished Engineer…

• less than a min read
Alok Jain , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Deepak Pant , video , ADS , assertions , IEV , Formal verification , IFV , Assertion-based verification

Verification

How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?

During the planning phase for SoC designs, teams have to choose whether to "make…

• 2 min read
High-Level Synthesis , IP , TLM , System Design and Verification , C-to-Silcon , IP re-use , re-use , reuse , SystemC , C-to-Silicon Compiler

Verification

Will Software Development Cause Another “Industrial” Revolution?

As you have read here before, Cadence has been working closely with Xilinx to create…

• 3 min read
zynq , edaForum , virtual prototypes , industrial , System-Level Design , Siemens , Virtual Platforms , Industrial Automation , Design Flows , Sanitas

Verification

India Needs Real-World Assertions Too

I've just returned from a week-long trip to India, spending most of my time at the…

• 4 min read
Functional Verification , Old Delhi , Noida , assertions , New Delhi , real-world assertions , India

Verification

Parallel Compilation for SystemC

One of the most common complaints about SystemC is that it takes too long to compile…

• 3 min read
Virtual System Platform , virtual platforms , GNU , parallel compilation , virtual prototypes , embedded software , C , LSF , compile , pallallel compile , make , SystemC , System Design and Verification

System, PCB, & Package Design 

What's Good About ADW’s Configuration Manager? The Secret's in the 16.5 Release!

The Allegro Design Workbench (ADW) Configuration Manager application is designed…

• 1 min read
PCB , data management , Allegro Design Workbench , Library flow , Team design , Allegro 16.5 , design data management , configuration manager , design , PCB design , SPB16.5 , Librarians , library , ADW , Allegro

Verification

Event Report: Club Formal Shanghai

The first "Club Formal" event in China was held in Shanghai on Oct. 21 2011, and…

• 2 min read
events , Verification IP , China , ABV , verification strategy , Functional Verification , ABVIP , formal , ADS , assertions , Club Formal , IEV , Assertion-Driven Simulation , Shanghai , Formal verification , IFV , Jin Tang , Assertion-based verification

Analog/Custom Design

SKILL for the Skilled: Introduction to Classes -- Part 4

In several previous postings we introduced the problem of solving the sudoku puzzle…

• 6 min read
Team SKILL , programming , Sudoku , object orientation , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL

Verification

Report on CDNLive! India 2011: Provocative Keynotes, Detailed Papers, and Robots…

Recently I had the honor of presenting the functional verification roadmap at CDNLive…

• 2 min read
Suman Ray , Low Power , Joe Hupcey III , ABV , Apurva Kalia , verification strategy , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Manu Chopra , Incisive , Lokesh Pundreeka , SVA , Lego , assertions , robot , MDV , Rubik's Cube , Formal verification , IFV , Assertion-based verification

System, PCB, & Package Design 

What's Good About Refresh, Copy Project, TCL in SCM? 16.5 Has a Few New Enhancements

There are several enhancements in the 16.5 System Connectivity Manager ( SCM ) /…

• less than a min read
PCB , SCM , Allegro Design Entry , Constraint-driven PCB Design flow , refresh option , Allegro 16.5 , ASA , Allegro System Architect (ASA) , Front-end PCB design , Design Entry , SPB16.5 , copy project , Schematic , Allegro , tcl

Verification

Shameless Promotion: Free Club Formal San Jose, Formal Scoreboard Webinar

Please join Team Verify and other D&V engineers for one or both of the following…

• 1 min read
scoreboard , ABV , methodology , verification strategy , Joerg Mueller , Functional Verification , Formal Analysis , formal , EDA360 , webinar , Club Formal , IEV , Formal verification , IFV , Assertion-based verification

Digital Design

CDNLive! Silicon Valley 2012 Abstracts Due November 11th, 2011

The Call for Papers for CDNLive! Silicon Valley 2012 is open now through Friday November…

• 1 min read
CDNLive , cadence , encounter , Cadence users , Digital Implementation , CDNLive!

Analog/Custom Design

Fred Discovers 1000x-10000x Speedup Using wreal Models

This is the second installment in an ongoing series of blog posts that includes an…

• 1 min read
real value , Verilog-AMS , analog , Mixed-Signal , analog behavoral , Verilog , Virtuoso , Fred , mixed signal , wreal , SPICE

RF Engineering

Guidelines for Maximizing Speed vs Accuracy for Harmonic Balance - Part 2

I am often asked for guidelines on maximizing speed vs. accuracy for SpectreRF…

• 3 min read
RF , RF Simulation , analog/RF , HB , Spectre RF , ADE-L , MMSIM , Virtuoso Spectre Simulator GXL , RF spectre spectreRF , Virtuoso Spectre Simulator XL , spectreRF , RF design , harmonic balance
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