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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Digital Design

Encounter Quick Tip: Dimming the Display with F12

I remember when I first started working with the Cooper & Chyan Technology (CCT)…

• 1 min read
dimming display , Encounterer Digital Implementation System , highlight , display , encounter , highlighted objects , darken display , quick tip , F12

Analog/Custom Design

Managing ECOs in Mixed Signal Designs

Imagine you are days away from completing the implementation of a fairly complex…

• 3 min read
ECO , Farhat , mixed signal design , CPF , Open Access , Floorplanning , ECOs , mixed-signal ECOs , Mixed-Signal , encounter , Virtuoso , oa , Mixed signal physical implementation

Verification

Amazon’s New Kindles: More Steps Toward the Paperback Computer

While I understand that a new Kindle Fire at $199 MRSP is significantly more than…

• 4 min read
Verification IP , RPP , SaaS , Joe Hupcey III , paperback computer , Cadence VIP portfolio , Kindle , system realization , VIP , EDA360 , EDA , VSP , Palladium XP , tablet , Hosted Design Solutions , Jim Hogan , Rapid Prototyping Platform , Amazon , Steve Leibson , cloud computing

Digital Design

Encounter Quick Tip: Finding Available Cell Masters with dbGet

When you first start using dbGet, many of your queries branch off the "top" keyword…

• 1 min read
dbGet , finding cells , cell masters , filler cells , encounter , Digital Implementation , Encounter Digital Implementation , quick tip

Verification

Technical Tip on How to Use HDL Assertions in e

While assertion callbacks have existed in Specman/e for several years now, several…

• 2 min read
IntelliGen , Specman , Incisive Enterprise Simulator , Incisive , e , SVA , e language , team specman , OOP , assertions , eRM , simulation , AOP , verification , Assertion-based verification

System, PCB, & Package Design 

What's Good About Allegro Database Locking? See for Yourself in 16.5!

Prior to the SPB16.5 release, multiple designers can edit and update the same Allegro…

• 2 min read
PCB , database locking , Allegro 16.5 , SPB , PCB Editor , Layout , design , PCB design , SPB16.5 , Allegro PCB Editor , Allegro

Verification

edaForum: Evolving Devices from “All in One” to “One for All”

This week I had the pleasure to attend and to present at the 11th annual edaForum…

• 7 min read
PCB , IMC , Intel , virtual platforms , edaForum , virtual prototypes , IP integration , System Development Suite , EDA360 , embedded software , Shirrmeister , IC/package co-design , one for all , hardware/software co-development , Power Analysis , System Design & Verification , Frank Schirrmeister , all in one , Eul , power , debugging , System Design and Verification

Verification

Missing Real-World Assertions in Computer-Land

I was reviewing the page view statistics on the Cadence Functional verification…

• 3 min read
uvm , ABV , outlook , Functional Verification , formal , assertions , Assertion-based verification

Verification

Virtual Platform UART Use Number 3: Using gdb to Debug a Software Application

This is the next installment in my series covering the uses of the venerable UART…

• 7 min read
virtual prototoypes , virtual platforms , TLM , GDB , debug , UART , embedded software , software , SystemC , debugging , linux , System Design and Verification

System, PCB, & Package Design 

What's Good About AMS Partial Design Simulation? It’s in the 16.5 Release!

Partial Design Simulation aims at unifying the PCB and simulation flow by enabling…

• 2 min read
PCB , "capture CIS" , AMS , AMS simulator , Capture CIS , Allegro 16.5 , Allegro 16.2 , partial simulation , PSPICE , design , AMS simulation , Design Entry , SPB16.5 , PCB Capture

Verification

ARM/Cadence Video: How ACE Coherency Adds Value and Verification Complexity

The number of licensees for ARM's Cortex-A15 CPU core is growing rapidly, particularly…

• 1 min read
Verification IP , ACE , Cortex-A15 , Functional Verification , video , VIP , interconnect monitor , ACE verification , cache coherency , coherency , ARM

Verification

Tech Tip: The “Show Me” Witness Trace Short-Cut for Design Bring-Up

In a prior Team Verify post, Application Engineer Bin Ju talked about several applications…

• 1 min read
show me , ABV , Functional Verification , Formal Analysis , formal , ADS , Chris Komar , witness trace , IEV , Assertion-Driven Simulation , simulation , Formal verification , IFV , Assertion-based verification

Verification

Rumors of SystemVerilog’s Death Have Been Greatly Exaggerated

Our friend and fellow blogger JL Gray recently published a post with the provocative…

• 2 min read
SystemVerilog , uvm , uvm world , universal verification methodology , UCIS , Accellera , JL Gray

System, PCB, & Package Design 

What's Good About Net Groups in Capture? Check Out the 16.5 Release and See!

A NetGroup is a collection of nets. The nets in a NetGroup can be scalar, vector…

• 2 min read
"capture CIS" , Allegro Design Entry , Capture CIS' , Design Entry CIS , OrCAD Capture Marketplace , electrical constraints , Capture CIS , Capture-CIS , Allegro 16.5 , design , OrCAD , Design Entry , net groups , SPB16.5 , NetGroup , PCB Capture , Schematic

Verification

Everything New is Old … Everything Old is New

The title of this post is taken from a fairly obscure 1982 record album (yes, vinyl…

• 2 min read
gate level , Functional Verification , LEC , RTL , DRC , LVS , EDA , old , gate-level , new , simulation

System, PCB, & Package Design 

What's Good About ADW’s Server? 16.5 Has a Few New Enhancements!

Some of the enhancements to the Allegro Design Workbench (ADW) 16.5 release were…

• 1 min read
PCB , Allegro Design Workbench , Library flow , Allegro 16.5 , design data management , design , "PCB design" , PCB design , SPB16.5 , Librarians , library , ADW , Allegro

Verification

Virtual Platform UART Use Number 2: Using telnet to Connect to a UART

Welcome to the next installment in my series about different ways to use the venerable…

• 4 min read
Virtual System Platform , TLM , virtual platform , UART , System Design and Verification , telnet , embedded software , xterm , virtual prototype , software , SystemC , linux , ESL

Analog/Custom Design

SKILL for the Skilled: Introduction to Classes -- Part 2

In the previous posting Introduction to Classes -- Part 1 we introduced the problem…

• 3 min read
Team SKILL , programming , object orientation , Virtuoso , Lisp , SKILL++ , SKILL

System, PCB, & Package Design 

What's Good About Power Pins in SCM? The Secret's in the 16.5 Release!

The 16.5 release of the Allegro System Connectivity Manager (SCM), also known as…

• 2 min read
SCM , Allegro Design Entry , Allegro 16.5 , SPB , BGA , Allegro System Architect (ASA) , design , Design Entry , SPB16.5 , FPGA , FPGA: PCB
CDNS - Fix Layout Hompage