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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

Verification

Video: Formal Verification Service Provider Oski Technology at DVCon 2011

While there was a lot (justifiable) buzz around the UVM 1.0 release, formal and assertion…

• 1 min read
ABV , verification strategy , Functional Verification , Formal Analysis , ABVIP , formal , Oski Technology , DVcon , IEV , Formal verification , IFV , verification

System, PCB, & Package Design 

What's Good About PCB PI Discontinuity Modeling? See For Yourself in SPB16.3!

The current Allegro PCB Power Integrity (PI) tool is fast, but not accurate enough…

• 1 min read
PCB SI , PCB , SI , PI , SPB16.3 , Integrity Check , discontinuity modeling , PCB PI , Signal Intregrity , SigXP UI , SPB 16.3 , Power Integrity , High Speed , PCB power integrity , SPB , electromagnetic , PCB Signal integrity , Allegro PCB Editor , SI analysis and modeling , Allegro

RF Engineering

My Favorite nport Settings for Spectre and SpectreRF

The nport component located in analogLib can be used in circuits for Spectre and…

• 4 min read
nport , RF , RF Simulation , Circuit simulation , RFIC , Spectre RF , Analog Simulation , nport settings , Spectre , analogLib

System, PCB, & Package Design 

What's Good About Allegro PCB Editor 3D Viewing? Oh My – Check Out SPB16.3!

The SPB16.3 Allegro PCB Editor has a new 3D Viewer! Viewing a 3D rendering of the…

• less than a min read
PCB , PCB Layout and routing , SPB16.3 , mechanical parts , Allegro 16.3 , SPB 16.3 , SPB , PCB Editor , Layout , design , "PCB design" , PCB design , Allegro PCB Editor , 3D viewer , Allegro

Verification

Video: DVCon 2011 Update From NextOp CEO Yunshan Zhu

At DVCon 2011 I had the opportunity to catch-up with NextOp's CEO Yunshan Zhu, where…

• less than a min read
Cadence Connections , NextOp , uvm , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Zhu , Palladium XP , SVA , DVcon , assertion synthesis , MDV , IEV , Formal verification , IFV , IES-XL

Verification

Save The Date: Free Webinar on Automated SoC Connectivity Verification This Thursday…

We interrupt our technically oriented blogging to shamelessly promote a free webinar…

• 1 min read
ABV , methodology , Functional Verification , formal , SoC Connectivity , IEV , Formal verification , IFV

Analog/Custom Design

Is China Ready for Next Generation Mixed-signal Design?

A Chinese design engineer told me that his manager once told him: "You do not have…

• 4 min read
China , mixed-signal ToT , tech on tour , abstraction , EDA360 , analog , Mixed-Signal , Convergence , intent , japan , Silicon Realization , mixed signal , SoCs

Analog/Custom Design

Rapid Analog Prototyping - Handcrafted Layout Gets a Needed Productivity Boost

As more and more custom/analog designs migrate to advanced process nodes (<65nm)…

• 4 min read
AMS , parasitic-aware design , PAD , RAP , Virtuoso IC6.1.5 , custom/analog , PCells , Advanced Node , analog , Constraint-driven , IC 6.1.5 , Mixed-Signal , Virtuoso , rapid analog prototyping , Custom IC Design , modgens , Virtuoso Layout Suite , parasitics

Analog/Custom Design

Early Analysis is Key – Parasitic-Aware Design

Decreasing geometries and increasing design complexity are making the task of designing…

• 3 min read
parasitic-aware design , Analog Design Environment , PAD , Virtuoso IC6.1.5 , IC 6.1.5 , ADE , Virtuoso , ADE-GXL , ADE-XL , parasitics

System, PCB, & Package Design 

What's Good About Capture OLE Object Placing? You Can Easily Do This in SPB16.3!

Object Linking and Embedding ( OLE ) support in SPB16.3 Allegro Design Entry CIS…

• 2 min read
"capture CIS" , SPB16.3 , Allegro Design Entry , Design Entry CIS , OrCAD Capture , SPB 16.3 , Capture CIS , Capture-CIS , OLE , SPB , design , OrCAD , object placing , Design Entry , PCB Capture

Digital Design

28 nm IC Design: The Devil Is In The Details

Smaller process technologies are enticing chip makers with bigger rewards from their…

• 4 min read
EDI , lithography , CMP , Litho , 28nm , DRC , metal thickness , LVS , Advanced Node , NanoRoute , encounter , via rules , LPE , digital , Silicon Realization , Digital Implementation , interconnect rules , Variation , stress , parasitics

Analog/Custom Design

Virtuoso IC6.1.5: Software and Fine Red Wine

Software, like fine red wine, can get better with age as well -- but it requires…

• 7 min read
AMS , parasitic-aware design , Low Power , Virtuoso IC6.1.5 , custom/analog , Analog Simulation , analog , Constraint-driven , IC 6.1.5 , Mixed-Signal , Virtuoso , mixed signal , Custom IC Design , DFM , parasitics

Verification

A Modest Proposal: Using Formal to Close Coverage Gaps

In my last blog post , I summarized some of our activities at DVCon and mentioned…

• 4 min read
NextOp , coverage , Functional Verification , Formal Analysis , formal , BugScope , Breker , DVcon , assertion synthesis , assertions , Closure , metrics , CVC , Formal verification

Verification

DATE Spotlights System Development University Investment in Europe

In this guest blog Markus Winterholer, R&D engineer at Cadence, explains why he's…

• 2 min read
university , DATE , Winterholer , UML , Daedalus , University Booth , VOCIS , System Design and Verification

RF Engineering

Tips for Simulating a Transmit Mixer in SpectreRF

Some typical questions that I receive from newer SpectreRF users are: How do I simulate…

• 8 min read
RF , RF Simulation , Spectre RF , ADE-L , Analog Simulation , MMSIM , spectreRF , Spectre , RF design , harmonic balance , mixer

Digital Design

Encounter Puzzler #3 Solution: Renaming a Net Logically

Once again, the Encounter Digital Implementation designer community has stepped up…

• 4 min read
conformal , dbGet , net renaming , encounter , Digital Implementation , Encounter Digital Implementation , puzzler , tcl

System, PCB, & Package Design 

What's Good About ADW’s Flow Manager? Check Out the ADW16.3 Release and See!

The ADW16.3 Allegro Design Workbench has a desktop cockpit that allows engineers…

• 4 min read
PCB , SPB16.3 , Allegro Design Entry , part developer , DEHDL , mechanical parts , Directive Lockhing , Allegro 16.3 , SPB 16.3 , High Speed , Allegro Design Workbench , Library flow , SPB , LRM , PCB Editor , Design Entry HDL , design data management , design , Library Revision Manager , "PCB design" , PCB design , Design Entry , ADW 16.3 , Allegro PCB Editor , Librarians , ConceptHDL , library , ADW , Schematic

Verification

Video: Optimizing Area and Power Using Formal Methods

At DVCon 2011, a paper presented by Freescale and Cadence described a truly novel…

• 1 min read
Low Power , ABV , methodology , Formal Analysis , formal , Freescale , Incisive , Chris Komar , DVcon , IFV

Verification

Video: New Cadence Verification IP Catalog (With Denali Inside!)

Clearly UVM 1.0 was the main story at DVCon last week, but there was other big news…

• less than a min read
uvm , Functional Verification , ABVIP , Cadence VIP portfolio , OVM , VIP , EDA360 , Verification IP modeling , DVcon , eRM
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