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Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

Thank You!

As the 2008 year comes to a close, I wanted to say Thank You! Thanks to the hard…

• 1 min read
PCB design

Verification

Video Demo: “irun” – The Way to run Simulations!

The irun utility provides a use-model to run simulations with Incisive Simulator…

• less than a min read
Functional Verification , Incisive Enterprise Simulator (IES)

System, PCB, & Package Design 

What's Good About the SPB16.2 PSpice Models? BSIM4 Support!

The SPB16.2 release now has new MOSFET device Model BSIM4 Support in PSpice PSpice…

• 4 min read
RF , SPB 16.2 , PCB design , BSIM4 , MOSFET

Verification

Is it Necessary to Improve the Quality of Consumer Electronics?

Fellow blogger Joe Hupcey passed along a link covering the recent launch of the BlackBerry…

• 4 min read
System Design and Verification , software acceleration , blackberry , Enterprise Manager , ISX

Verification

Constraint Layering - Fine Tuning Your Environment - Part 2

In my last post , I talked briefly about constraint layering in which I gave an extremely…

• 4 min read
IEEE 1647 , Specman , verification strategy , Verification methodology , Functional Verification , Testbench simulation , e , Aspect Oriented Programming , IES , AOP

Analog/Custom Design

Video Chat with Lead Architect of Virtuoso Accelerated Parallel Simulator

Virtuoso Accelerated Parallel Simulator was just released and I asked Ilya Yusim…

• 1 min read
mixed-signal simulators , MMSIM , Circuit Design , Simulators , Custom IC Design , custom design technology

Digital Design

Become an Encounter Digital Implementation System Specialist and Win Cool Prizes

Last week, we announced the Encounter Digital Implementation System along with a…

• less than a min read

Verification

New Technical Blog on e & Specman Technology

Specmaniacs of the world: rejoice! Members of Team Specman have just launched their…

• less than a min read
IEEE 1647 , Specman , e

Verification

Constraint layering - Fine Tuning Your Environment - Part 1

In today's environment of ever growing complexity and ever shrinking schedules,…

• 3 min read
IEEE 1647 , SystemVerilog , Specman , verification strategy , Verification methodology , Object Oriented Programming , Functional Verification , e , OOP , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP

Verification

New e / Specman Workshops Available Now

In response to the continual growth in the e /Specman user community, Team Specman…

• 2 min read
workshops , IEEE 1647 , Specman , metric driven verification (MDV) , Functional Verification , Testbench simulation , MDV techtorial , OVM e , Coverage-Driven Verification , e , Kit , coverage driven verification (CDV) , eRM , IES

Verification

New Blog - All About e & Specman

End-users of e , Specman, Incisive Enterprise Simulator (IES), e RM/OVM e , and…

• 1 min read
IEEE 1647 , Specman , verification strategy , metric driven verification (MDV) , Functional Verification , Testbench simulation , OVM e , Coverage-Driven Verification , e , coverage driven verification (CDV) , eRM , Incisive Enterprise Simulator (IES) , IES

System, PCB, & Package Design 

What's Good About SPB16.2 OrCAD Capture? Many Usability Enhancements!

There are enormous usability updates in the SPB16.2 release of OrCAD Capture. From…

• 7 min read
SPB 16.2 , OrCAD , PCB design

Analog/Custom Design

What's New With Virtuoso?

If you were wondering what's new with Virtuoso you may want to check out the latest…

• less than a min read
MMSIM , Floorplanning , Virtuoso IC 6.1.3 , Virtuoso , RF design , Custom IC Design

Verification

Metric Driven System Level Verification

I have the great honor of introducing a wonderful paper on system level verification…

• 1 min read
System Design and Verification , ARC International , ISX

Verification

VMM Users -- Welcome to the OVM!

VMM users -- welcome to the OVM! We've been talking together about the benefits…

• 3 min read
SystemVerilog , Verification methodology , Functional Verification , OVM , VIP , e , eRM , OVMWorld

Digital Design

3 Reasons Why You Will Want to Download Encounter 8.1

Today is a big day in Digital Implementation land here at Cadence. Looking around…

• less than a min read
Flows , SoC-Encounter 8.1 , Low-Power , Digital Implementation , Floorplanning and Prototyping

System, PCB, & Package Design 

What's Good About the SPB16.2 Cross Referencer? Active Links in the Schematic!

That's right - an often requested feature from several customers has now been implemented…

• 2 min read
SPB 16.2 , PCB design

Digital Design

Innovate Your Way Out of Recession With the New Encounter!

It's official! The U.S. economy has been in a recession for the past year. …

• 2 min read
Static timing analysis , Early Rail Analysis , SoC-Encounter , Digital Implementation forums , First Encounter , SoC-Encounter 8.1 , Signoff Analysis , STA , encounter , Cadence Encounter Power System , Digital Implementation , CeltIC NDC , Global Timing Debug , Encounter Timing System , SSTA , Floorplanning and Prototyping , "SoC-Encounter"

Verification

News From the IP '08 Conference

My colleagues on the Verification IP team have been honored to present at the annual…

• 3 min read
HW/SW , metric driven verification (MDV) , Functional Verification , Cadence VIP portfolio , VIP , Coverage-Driven Verification , Multi-domain verification: HW/SW co-verification , ISX (Incisive Software Extensions) , Verification IP modeling , ISX
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