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Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
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System, PCB, & Package Design 

Brad Griffin Speaks at DesignCon - Give Him a Listen!!

If you were not lucky enough to be atDesignCon this week, and many of us were not…

• less than a min read
PDN , cadence , Digital SiP design , Advanced Node , IC Packaging & SiP design , SerDes , IC design , IC Package Physical layout and co-design , design chain

System, PCB, & Package Design 

What's Good About ASA Differential Pair Swapping? - The Secret's in the SPB16.2 Release

And the new features list just keeps going on and on - it's terrific! In the SPB16…

• 1 min read
SPB 16.2 , ASA , PCB design , differential Pair Swapping , Allegro

Verification

Exploring the Virtual Platform Part 3

Welcome to part 3 of the "Exploring the Virtual Platform" series. For readers just…

• 4 min read

Analog/Custom Design

Virtuoso Advanced Parallel Simulation Leveraging Parallelization Technology.

There is an interesting interview with Nebabie Kebebew, Sr. Product Marketing Manager…

• less than a min read
mixed-signal simulators , Chip-level simulation , MMSIM , Block-level simulation , Virtuoso , AMS simulation , Circuit Design , Simulators , Custom IC Design , custom design technology

Verification

Report From DesignCon 2009

This week the " DesignCon " show is in town (<= 10 minutes from the Cadence campus…

• 2 min read
DesignCon , Functional Verification

Verification

Good Article Alert: End "EDA Bashing"

Allow me to direct your attention to a most welcome article in EDA DesignLine written…

• less than a min read
Functional Verification , edadesignonline , EDA

SoC and IP

Web Survey: LP DDR and DDR3 DRAMs

LP DRAMs and PC DDR3 DRAMs: Vendors’ Portfolios Fill out Slowly (LP) and Rapidly…

• 3 min read

Verification

Incisive Software Extensions (ISX) vs Co-Verification Link (CVL)

Team Specman has been doing a great job supplying nifty tech tips and other useful…

• 3 min read
CVL , Co-verification link , System Design and Verification , Specmen , Incisive Software Extensions , ISX

Verification

Linking C and e: The Co-Verification Link

[Join Team Specman in welcoming guest blogger Jason Andrews. Jason is a recognized…

• 3 min read
Specman , HW/SW , C , e , ISX , Incisive Enterprise Simulator (IES) , Jason Andrews , IES

Verification

"...Yes, Virginia there is a Specman"

I usually try to visit many of our customers in Europe (and other parts of the world…

• 3 min read
SystemVerilog , IntelliGen , Specman , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , Coverage-Driven Verification , e , coverage driven verification (CDV) , Aspect Oriented Programming , eRM , AOP

Verification

Interview With Cadence Verification IP Architect Levent Caglar

Even in these challenging economic times, interest in Verification IP ("VIP") has…

• less than a min read
verification strategy , Functional Verification , VIP , Levent Caglar

RF Engineering

SpectreRF Turbo: Parasitic Reduction

I wanted to share some experiences I had with SpectreRF-Turbo and Parasitic reduction…

• 1 min read
Virtuoso Spectre , Spectre RF , Parasitic Reduction , RF Block Simulation , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , RF design , harmonic balance , Turbo

Digital Design

Demo and Interview: The Encounter Foundation Flow

One of the new features I mentioned in my previous entry on 3 Reasons You'll Want…

• 5 min read
Flows , 8.1 , Encounter Digital Implementation

Digital Design

A dbGet Code Example

I've been having a lot of fun with power switch cells lately. That's a whole other…

• 3 min read
database access , SoC-Encounter , dbGet , dbSet , Digital Implementation

SoC and IP

Taiwan Mixing it up with DRAMs, Part II..Acceptance?

Mirrors Worldwide Government's Increasing Role in Business and the Economy; “Cash…

• 4 min read

RF Engineering

Noise and Jitter Analysis for PLL-Based Frequency Synthethiser Using SpectreRF

Cadence will present SpectreRF Noise aware PLL flow latest enhancements at the DesignCon…

• 1 min read

System, PCB, & Package Design 

What's Good About a Table of Contents Generator? - Download SPB16.2 and See!

It's here! It's really here!!! I've spoken with many customers over the past several…

• 5 min read
SPB 16.2 , TOC , table of contents , PCB design

Verification

Tech Tip: Avoiding "Error! Integer Overflow" With Incisive Simulator

While simulating a VHDL design with Incisive Simulator, if an integer overflow is…

• 1 min read
NCVHDL , Functional Verification , Incisive Enterprise Simulator (IES) , IES

Verification

"ClubT" Newsletter Issue #3 Just Posted

Specmaniacs and Other Trailblazers, The latest edition of the 'ClubT ' newsletter…

• less than a min read
IEEE 1647 , SystemVerilog , IntelliGen , Low Power , Specman , HW/SW , verification strategy , Verification methodology , metric driven verification (MDV) , Functional Verification , Cadence VIP portfolio , Testbench simulation , OVM , VIP , OVM e , Coverage-Driven Verification , CDV , Multi-domain verification: HW/SW co-verification , e , Enterprise Manager , Enterprise Planner , ISX (Incisive Software Extensions) , Plan and metrics management , coverage driven verification (CDV) , Aspect Oriented Programming , ISX , System Verification , Incisive Enterprise Simulator (IES) , IES , AOP
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