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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

Digital Design

Get Early Silicon Learning to Accelerate Yield Ramp-up

How important is it for your advanced node products to get early silicon learning…

• 2 min read
DNA , pattern analysis , machine learning , silicon learning , yield , test chip , design for manufacturing , DFM

Whiteboard Wednesdays

Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 2

In this week's Whiteboard Wednesday, Tom Hackett continues his explanation of neural…

• less than a min read
Whiteboard Wednesdays , neural networks

Analog/Custom Design

Virtuosity: Can I Plot Signals with Different Axis Units in the Same Window?

Have you been frustrated trying to drag signals around in Virtuoso Visualization…

• 1 min read
virtuoso visualization and analysis , Virtuoso Analog Design Environment , Analog Design Environment , ViVA

Breakfast Bytes

Supercomputers

HPC, or high-performance computing, is one of the big focus areas for semiconductors…

• 9 min read
Intel , top 500 list , top500 , supercomputer

Analog/Custom Design

Virtuosity: CDNLive India—Our Window to KYC!

In line with the recently-implemented mandate in India requiring banks and financial…

• 1 min read
CDNLive India 2017 , Cadence Help Future , Virtuosity , Virtuoso Video Diary , Cadence Help 3.0

Breakfast Bytes

What's For Breakfast? Video Preview December 11th to 15th 2017

https://youtu.be/Ar98HS9Dnow Coming from Union Square, San Francisco (camera Carey…

• less than a min read
government , risc-v , International Electron Devices Meeting , cots , risc-v workshop , Aviation , IEDM

SoC and IP

Book Your CES Meetings Now!

Want to see the exciting technology that is behind some of the biggest innovations…

• 1 min read

Breakfast Bytes

Formal Verification Sign-Off...and the First Text Message

Recently, it was the 10th annual Jasper User Group meeting (see my earlier post Jasper…

• 8 min read
Jasper User Group , JUG , formal , Oski Technology , Formal verification

RF Engineering

How to Set Up and Plot Large-Signal S Parameters?

Large-signal S-parameters (LSSPs) are an extension of small-signal S-parameters and…

• 1 min read
RF Simulation , Spectre RF , Virtuoso ADE , Virtuoso

Verification

Perspec System Verifier is #1 in Portable Stimulus in 2017 User Survey

It’s now official: Perspec System Verifier is rated the #1 product in the #1 category…

• 3 min read

Breakfast Bytes

Silexica: Mastering Multicore

Since the invention of the microprocessor, it was a dream that it would be possible…

• 9 min read
silexica , Tensilica , multicore

Breakfast Bytes

Jasper User Group: How to Be a Formal Verification Lead

Recently, it was the 10th annual Jasper User Group meeting (see my earlier post Jasper…

• 7 min read
Intel , Jasper User Group , JUG , formal , verification

RF Engineering

Triple Beat Analysis: What, Why & How?

The Triple Beat analysis is similar to Rapid IP2/IP3 analysis except that it uses…

• 2 min read
Virtuoso ADE , Virtuoso , Spectre , RF design

The India Circuit

Hello, My Name Is Anna. Can I Help You?

Chatbots are annoyingly familiar to anyone who has shopped online. The distracting…

• 3 min read
chatbot , artificial intelligence , Wysa , AI

Verification

Check Again: Cadence Announces Release of the First PCIe 5.0 VIP—With TripleCheck…

On November 28, 2017, Cadence announced the release of the first available PCIe®…

• 1 min read
Functional Verification , PCI-e , announcement , TripleCheck

Breakfast Bytes

Chips and Technologies: The First Fabless Company

As part of writing Fabless: the Transformation of the Semiconductor Industry a couple…

• 5 min read
fabless , chips and technologies , foundry

Breakfast Bytes

November Breakfast Buffet

https://youtu.be/paqvuLll4pM Coming from the rain on the roof of Cadence building…

• less than a min read
Jasper User Group , Rutenbar , breakfast buffet , JUG , Kaufman Award , fabless , alto , chips and technologies , social engineering

Whiteboard Wednesdays

Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 1

In this week's Whiteboard Wednesday, Tom Hackett explains neural network basics using…

• less than a min read
Whiteboard Wednesdays , neural networks

Breakfast Bytes

CCIX Update: TSMC, Xilinx, Cadence, Arm...and Jasper

CCIX (pronounced see-six) is the Cache Coherent Interconnect for Accelerators. I…

• 5 min read
Jasper User Group , JUG , formal , ccix , TSMC , xilinx , ARM
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