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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

Take Your Via Structures from Ordinary to Exceptional with 16.6 IC Packaging Advanced…

Via structures—those reusable patterns of conductor clines and vias designers rely…

• 5 min read
IC Packaging and SiP Design , SiP , IC Packaging , packaging , Analog and RF SiP design , 16.6 , IC package design , APD , wirebonds , APR , IC Packaging & SiP design , BGA , Allegro Package Designer , IC packaging documentation , early adopter , APD 16.6 , SiP Layout , wirebonding , IC Package Physical layout and co-design

SoC and IP

Great Progress with Ethernet Standards Development

The IEEE 802 local area networking standards committee held its plenary meeting in…

• 2 min read
controller IP , Verification IP , PoDL , 802.3bp , Design IP , IP , cadence , 802.3bs , PHY , 400Gpbs , 40Gbps , Automotive Ethernet , 802.3bt , 802.3bq , 802.3br , 100Gbps , 802.3bu , IEEE 802.3 , Ethernet , 802.3bm , Marris , 802.3bj , semiconductor IP , Ethernet PHYs , Power over Data Lines , Power over Ethernet

Verification

Covering Edges (Part I) – Cool Automation

With random generation, most of the fields are due to be quite well covered. If…

• 2 min read
AF , e language , Funcional Verification , functional coverage , coverage driven verification (CDV) , Aspect Oriented Programming

Analog/Custom Design

SKILL for the Skilled: SKILL++ hi App Forms

One way to learn how to use the SKILL++ Object System is by extending an application…

• 10 min read
layout hierarchy , Jim Newton , schematic hierarchy , object orientation , Layout , Virtuoso , object system , software development , design hierarchy , SKILL++ , SKILL , Schematic

Verification

Accelerating Code Coverage Using Palladium XP Rapid Adoption Kit

Code coverage is an effective tool in the verification process, giving insights into…

• 1 min read
IMC , System level verification and validation with Palladium XP , Rapid Adoption Kits , Palladium XP , UniCov Databases , Accelerated Code Coverage , RAKs , Accelerated Coverage , Assertions and Functional Coverage with covergroups.

System, PCB, & Package Design 

Optimize Your PCB Decoupling Capacitors and Remain a Person of Integrity

How much integrity is too much? If your PCB designs apply one or more decoupling…

• 2 min read
PDN , Power Integrity , High Speed , OptimizePI , Power Delivery Network , power-aware SI , decap , Allegro Sigrity

Analog/Custom Design

SKILL for the Skilled: Simple Testing Macros

In this post I want to look at an easy way to write simple self-testing code. This…

• 5 min read
Team SKILL , programming , shuffle , Jim Newton , SKILL for the Skilled , macros , Lisp , SKILL++ , SKILL

Verification

High-Level Synthesis Now Spans the Datapath-Control Spectrum

When we talk to prospective high-level synthesis (HLS) customers, one of the slides…

• 1 min read
antenna interface controller , controll logic , ITRI , NAND flash controller , C-to-Silcon , Freescale , System C , rtl compiler , data access controller , datapath , high level synthesis , Fujitsu Semiconductor

System, PCB, & Package Design 

Signal Integrity Analysis of Serial Data Channels—A Complete Solution Using Allegro…

Back in the day, when challenged to transfer data faster, we increased the width…

• 1 min read
Serial link analysis , High Speed , IBIS-AMI , Signal Integrity , SI analysis and modeling , SystemSI , Allegro Sigrity

Analog/Custom Design

Virtuosity: 12 Things I Learned in October by Browsing Cadence Online Support

Lots of routing, a little AMS, and finishing off with some fun... Application Notes…

• 3 min read
SystemVerilog , AMS , PAD , Virtuoso Space-based Router , VSR , Routing , Spectre , mixed signal

Digital Design

11 Things I Learned by Browsing Cadence Online Support

I guess by now most of us are already familiar with Rapid Adoption Kits (RAKs). These…

• 3 min read
Digital Implementation forums , How To , Cadence EDI System , power routing , Floorplanning , encounter digital implementation system , beginner , NanoRoute , training , Appnotes , Top Ten , digital implementation , Cadence Encounter Power System , GigaOpt , Digital Implementation , Encounter Digital Implementation , crosstalk , app notes , high performance , Rapid Adoption Kits , encounter power system , OpenAccess , Floorplanning and Prototyping , RAKs , FlipChip

Verification

High-Level Synthesis—What Expertise Is Needed for Micro-Architecture Tradeoffs?

My most recent blog post mentioned how utilizing new algorithms together with high…

• 5 min read
RAM , micro-architecture , hardware , C-to-Silcon , C , SystemC , HLS , C++

System, PCB, & Package Design 

What's Good About Capture’s NetGroup Update? 16.6 Has a Few New Enhancements!

The 16.6 release of OrCAD Capture provides a few enhancements in the area of NetGroups…

• 1 min read
capture , Cadence Design Systems , Allegro 16.6 , cadence , hierarchical net groups , OrCAD Capture , 16.6 , Capture CIS , Capture-CIS , hierarchical schematics , SPB , design , NetGroups , OrCAD , Grzenia , net groups , NetGroup , Schematic , hierarchical block

System, PCB, & Package Design 

What's Good About FPGA System Planner and Netgroups? 16.6 Has It!

Beginning with the 16.6 SPB release, FPGA System Planner (FSP) can create net groups…

• 2 min read
PCB , Cadence Design Systems , FPGA: ASIC Prototype , Allegro 16.6 , cadence , FPGA-PCB Co-Design , FPGA System Planner , 16.6 , FPGAs , PCB Editor , setup , Layout , Front-end PCB design , design , NetGroups , FSP , PCB design , Constraints , Grzenia , net groups , NetGroup , FPGA , FPGA Pin Assignment , FPGA: PCB

Verification

Accelerated Code and Functional Coverage Using Palladium XP

Code coverage is an effective tool in the verification process—giving insights into…

• 2 min read
IMC , Cadence Online Support , UXE , Palladium XP , Incisive Verification Environment , support.cadence.com , Accelerated SV Covergrooups , Accelerated Coverage , IES

Verification

Coverage Unreachability UNR App - Rapid Adoption Kit

The Cadence Incisive Enterprise Verifier (IEV) team recently developed a self-help…

• 3 min read
coverage , Unreachability , RAK , UNR , IEV , Incisive Enterprise Simulator (IES) , Formal verification

Verification

Generic Dynamic Run-Time Operations with e Reflection, Part 1

Untyped Values and Value Holders The reflection API in e not only allows you to perform…

• 3 min read
AF , Functiional Verification , e language , Funcional Verification , coverage driven verification (CDV) , Aspect Oriented Programming , reflection

Analog/Custom Design

IC6.1.6 Virtuoso Space-Based Mixed-Signal Router (VSR)

Virtuoso Space-Based Router (VSR) is routing solution integrated into the Virtuoso…

• 4 min read
Technology on tour , MS ToT , VSR , mixed-signal ToT , mixed-signal training , Router , tech on tour , Open Access , analog/mixed-signal , OA: OpenAccess , tech-on-tour

System, PCB, & Package Design 

What's Good About DEHDL’s Variant Editor? 16.6 Has Several New Enhancements!

The recent 16.6 QISR-2 for Allegro Design Entry HDL has new capabilities for the…

• 1 min read
Cadence Design Systems , Allegro Design Entry , Allegro 16.6 , cadence , varient editor , 16.6 , SPB , design , Grzenia , ConceptHDL , Schematic , Allegro
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