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Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog
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Blog - Post List

Latest blogs

SoC and IP

Tensilica Team Wins DAC 2015 Best Paper Award

Cadence’s Tensilica team was honored with the Best Paper Award at the IP track at…

• 1 min read
IP , Chris Rowen , ip cores , vision , imaging , image processing

Analog/Custom Design

Virtuosity: 14 Things I Learned in May 2015 by Browsing Cadence Online Support

Cadence Documentation 1. Cadence Documentation Survey Cadence is committed…

• 4 min read
ADE XL , Virtuoso , Spectre

Verification

Designing a Google Ara Module and Worrying About MIPI UniPro?

So you've looked at Google project ARA and you have the most brilliant idea for a…

• 1 min read
Verification IP , UniPro , Ara , VIP , MIPI , google , TripleCheck

Verification

Aargh!!! How Can I Read Arguments from the Command Line Without argv?

Many times a user would like to be able to modify the behavior of a program based…

• 3 min read
Specman , Functional Verification , e language , simulation

Verification

Multi-Language Verification Environment (#4)—Multi-Language Hierarchy

In the previous posts in this series on Multi-Language Verification Environment,…

• 2 min read
uvm , Functional Verification , e , universal verification methodology , e language , multi-language , verification

Digital Design

Five-Minute Tutorial: The Innovus Standard Flow

Hi Everyone, Last week I highlighted a video featuring Innovus User Interface…

• less than a min read
design flow , Digital Implementation , Innovus , five minute tutorial

Verification

Multi-Language Verification Environment (#3) – Connecting UVM Scoreboard to a Multi…

In the previous blog post , we demonstrated connecting a checker implemented in SystemVerilog…

• 3 min read
SystemVerilog , uvm , multi-language verification , UVM Scoreboard , verification

Verification

DAC 2015 – Join Us to Experience the Continuum of Verification and System Development…

The biggest yearly event in electronic design automation (EDA) is due to take over…

• 8 min read
cadence , EDA , Moscone Center , DAC 2015 , verification , system development

Verification

It’s Time to Modernize Debug Data and It’s Happening at DAC

“The leading edge is 1 million gates.” That was the news when we approved IEEE Verilog…

• 2 min read
Verdi , debug , simvision , VCs , Indago , Debussy , Questa , Incisive Enterprise Simulator (IES) , IES

Whiteboard Wednesdays

Whiteboard Wednesdays—What's a Configurable Processor?

In this week's Whiteboard Wednesdays video, Chris Rowen discusses the basics of Tensilica…

• less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , Tensilica , configurable processor

Digital Design

Five-Minute Tutorial: Innovus User Interface Tips

Hi Everyone, No doubt by now you have heard about the Innovus Implementation System…

• less than a min read
UI , Digital Implementation , Innovus , five minute tutorial

Verification

How Ethernet Standards Are Born

I attend IEEE 802.3 Ethernet standards meetings and blog about them from time to…

• 5 min read
Verification IP , 802.3bp , Ethernet standards , Automotive Ethernet , Ethernet , 802.3 , Marris

Verification

Multi-Language Verification Environment (#2) – Passing Items on TLM Ports, Using…

In the previous blog post , we created a simple multi-language verification environment…

• 3 min read
IEEE 1647 , uvm , methodology , Functional Verification , e , universal verification methodology , e language , multi-language , verification

Verification

Multi-Language Verification Environment—Getting First Run in Few Minutes

Seems that by now, every one in the industry realizes that multi-language verification…

• 2 min read
uvm , methodology , e , e language , UVC , multi-language

Verification

Specman deep_copy()—Creating Too Many Structs

This blog starts with a description of a debugging session of a mysterious behavior…

• 3 min read
Specman , debug , e , Funcional Verification , ClubT

SoC and IP

Three Steps for USB Application Success – Design, Verify, Certify

With the USB protocol being so popular nowadays (and frankly speaking, was there…

• 2 min read
Design IP , host , cadence , controller , PHY , OTG , USB , Dual Mode , ip cores , Dual Role , device

Whiteboard Wednesdays

Whiteboard Wednesdays - DDR4 Bank Grouping

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty continues his discussion…

• less than a min read
Whiteboard Wednesdays , DDR4 , memory IP , DDR4 bank grouping

System, PCB, & Package Design 

What's Good or Not So Good About Cadence Documentation? Here’s Your Chance to Let…

Most of our customers use the product documentation, Help, and Cadence Online Support…

• less than a min read
COS , Cadence Design Systems , Cadence Online Support , Cadence Help , Cadence documentation

SoC and IP

IP is BIG at the Design Automation Conference, June 7-11, in San Francisco

Think that DAC is all about EDA tools? Not anymore. This year there are over 100…

• 2 min read
controller IP , Verification IP , DSP , Design IP , IP , Chris Rowen , Rowen , IP blocks , ip cores , Tensilica , DAC 2015 , Design IP and Verification IP
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