Cadence Blogs

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate 23 Jun 2026 • 3 min read

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate 22 Jun 2026 • 8 min read

featured , physical ai , HGR , AI , Honda

The New ASK Portal Brings a Smarter, Faster, and More Intuitive Experience

Finding the right support content should be simple, fast, and intuitive. The new…

Corporate 22 Jun 2026 • 2 min read

featured , customer support , New ASK Portal , ASK Gen AI

The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate 18 Jun 2026 • 7 min read

featured , infrastructure ai , agentic ai , Principled Simulation , physical ai

cdns - all_blogs_categories

All 6403
Corporate News 264
Life at Cadence 204
Academic Network 169
Analog/Custom Design 804
Artificial Intelligence 27
Cloud 23
Computational Fluid Dynamics 374
Data Center 59
Digital Design 458
Learning and Support 62
RF Engineering 116
SoC and IP 435
System, PCB, & Package Design 1015
Verification 1326
Cadence Japan 18
Physical Systems Simulation 14

CFD（数値流体力学) 45
中文技术专区 9
カスタムIC／ミックスシグナル 199
PCB、IC封装：设计与仿真分析 136
PCB解析／ICパッケージ解析 44
PCB設計／ICパッケージ設計 61
RF /マイクロ波設計 45
Spotlight Taiwan 64
The India Circuit 93
定制IC芯片设计 79
データセンター 7

Whiteboard Wednesdays 253

Blog - Post List

Latest blogs

Verification and the Need for Collaboration

Earlier this week I was at the ARM TechCon in Santa Clara, a show that gets better…

tomacadence 28 Oct 2011 • 2 min read

NextOp , ARM Techcon , uvm , collaboration , Zocalo , Functional Verification , Standards , partnerships , VA , EDA360 , EDA , Duolog , verification alliance , UCIS , AMIQ

Report: Formal Analysis Papers at CDNLive India 2011

On October 19, 2011 in Bangalore, India more than 800 engineers across all domains…

TeamVerify 26 Oct 2011 • 3 min read

ABV , CDNLive , Functional Verification , Formal Analysis , ABVIP , formal , Lokesh Pundreeka , ADS , metric-driven verification , assertions , MDV , IEV , Assertion-Driven Simulation , Formal verification , IFV , India , Assertion-based verification

What's Good About PCB SI IOCell Editor in Model Editor? 16.5 Has a Few New Enhancements

There are currently multiple options for model editing in the Allegro PCB SI environment…

Jerry GenPart 25 Oct 2011 • 2 min read

PCB SI , PCB , SI , I/O , SiP , Signal Intregrity , Digital SiP design , SigXP UI , PCB Signal and power integrity , High Speed , Allegro 16.5 , SigWave , Signal Integrity , Allegro PCB SI , PCB design , SPB16.5 , IOCell Editor , SI analysis and modeling , model editor , library , Allegro

Virtual Platform UART Use Number 4: Connecting to an RTOS Tracing Framework

This is the last installment of my series on different uses for the UART in Virtual…

jasona 24 Oct 2011 • 4 min read

Virtual System Platform , virtual platforms , Quantum Platform , virtual prototypes , dining philosophers , UART , System Design and Verification , RTOS tracing , QP , software , qspy

Come See How to Connect SystemVerilog and SystemC Using UVM

All pun-tastic references aside, connecting SystemVerilog and SystemC is becoming…

Adam Sherer 18 Oct 2011 • 1 min read

SystemVerilog , uvm , OVM ML , Functional Verification , webinar , multi-language , SystemC , IES

What's Good About APD’s Die Abstract Compare? You’ll Need the 16.5 Release to See

In the distributed co-design environment in the SPB16.5 Allegro Package Designer…

Jerry GenPart 18 Oct 2011 • 4 min read

PCB , SiP , IC Packaging , packaging , SiP Design , APD , Allegro 16.5 , IC/package co-design , PCB Editor , Allegro Package Designer , Layout , design , PCB design , die abstract compare , SPB16.5 , die abstract , Allegro

Analog/Custom Design

SKILL for the Skilled: Introduction to Classes -- Part 3

In the previous posting Introduction to Classes -- Part 2 we saw the high level…

Team SKILL 17 Oct 2011 • 8 min read

Team SKILL , programming , Sudoku , classes , IC 6.1.5 , object orientation , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL

Too Many Missing Real-World Assertions?

Well, here I am embarking on my fifth post in which I point out illogical situations…

tomacadence 14 Oct 2011 • 4 min read

ABV , Functional Verification , formal , assertions , Assertion-based verification

Team Allegro to Preview PCB 3D Full-Wave Technology at EPEPS 2011

At the Electrical Performance of Electronic Packaging and Systems conference ( EPEPS…

TeamAllegro 14 Oct 2011 • 1 min read

PCB , UIUC , EMS2D , EPEPS , interconnects , PCB PI , packaging , 3D extraction , PCB Signal and power integrity , Signal Integrity , full-wave , Allegro PCB SI , PCB design , EM , EMS3D , DDR3 , Allegro

Formal Verification with Asynchronous Clocks

Many designs have multiple independent clock inputs with different frequency specifications…

TeamVerify 13 Oct 2011 • 2 min read

ABV , asssertion-based verification , Joerg Mueller , Verification methodology , Functional Verification , Formal Analysis , formal , SVA , PSL , assertions , IEV , Formal verification , IFV , verification

What's Good About Allegro GRE Disabling Bundle Compression? It’s in the 16.5 Release

With the SPB16.5 release of Allegro Global Route Environment (GRE) , you can now…

Jerry GenPart 11 Oct 2011 • 1 min read

PCB , PCB Layout and routing , bundle compression , global route , Routing , Allegro 16.5 , PCB Editor , Layout , design , PCB design , SPB16.5 , Allegro PCB Editor , GRE , disabiling bundle compression , Allegro

Automating UVM to Tackle Insidious HW/SW Bugs

You've just sat through a 2-hour program review. The 30 minutes you spent describing…

Adam Sherer 10 Oct 2011 • 1 min read

SystemVerilog , uvm , bugs , Duolog , universal verification methodology , Accellera VIP TSC , David Murray , IES

RF Engineering

Guidelines for Maximizing Speed vs Accuracy for Harmonic Balance - Part 1

Greetings, I am often asked for guidelines on maximizing speed vs. accuracy for SpectreRF…

Tawna 7 Oct 2011 • 2 min read

RF , RF Simulation , analog/RF , APS , HB , Spectre RF , Analog Simulation , Virtuoso Spectre Simulator GXL , ADE , Virtuoso Spectre Simulator XL , spectreRF , RF design , harmonic balance

What's Good About Allegro PCB Router HDI Via Tangency? Check Out 16.5!

High Density Interconnect (HDI) techniques are increasing in the PCB domain. HDI…

Jerry GenPart 5 Oct 2011 • 1 min read

PCB , blind vias , global route , Routing , layer stacks , High Speed , via tangency , Allegro 16.5 , PCB Editor , High-Density Interconnect , Layout , via , design , miniaturization , PCB design , SPB16.5 , Allegro PCB Editor , buried vias , HDI , microvia , Allegro

Free Webinar Thursday 10/13 -- Automating Assertion Generation for Simulation, Formal…

Everyone can agree that Assertion-Based Verification (ABV) is a powerful methodology…

TeamVerify 5 Oct 2011 • 1 min read

NextOp , Joe Hupcey III , ABV , methodology , interview , Formal Analysis , BugScope , Incisive , webinar , DVcon , assertion synthesis , assertions , IEV , Yuan Lu , Formal verification , IFV , Assertion-based verification , IES-XL

17M Gates in 8 Months with 2 Designers -- What is Your ROI for Higher-Abstraction…

In their presentation at the recent SystemC Japan conference, Renesas Micro Systems…

Jack Erickson 4 Oct 2011 • 3 min read

time-to-market , High-Level Synthesis , verification turnaround , TLM , C-to-Silcon , ROI , System-Level Design , SystemC , C-to-Silicon Compiler , productivity

Digital Design

Encounter Quick Tip: Dimming the Display with F12

I remember when I first started working with the Cooper & Chyan Technology (CCT)…

BobD 30 Sep 2011 • 1 min read

dimming display , Encounterer Digital Implementation System , highlight , display , encounter , highlighted objects , darken display , quick tip , F12

Analog/Custom Design

Managing ECOs in Mixed Signal Designs

Imagine you are days away from completing the implementation of a fairly complex…

Benatcdn 29 Sep 2011 • 3 min read

ECO , Farhat , mixed signal design , CPF , Open Access , Floorplanning , ECOs , mixed-signal ECOs , Mixed-Signal , encounter , Virtuoso , oa , Mixed signal physical implementation