Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

Domain-Specific Computing 2: The End of the Dark Ages

Yesterday looked at how general-purpose computer architecture changed during the…

• 5 min read
computer architecture , domain specific computing

System, PCB, & Package Design 

Teardrops and Tapers – Improving Manufacturability and Yield Automatically

Teardrops (also called fillets) are the blending area of a cline entry into a pad…

• 4 min read
PCB Layout and routing , IC Packaging and SiP Design , PCB Editor , Allegro PCB Editor

Breakfast Bytes

Domain-Specific Computing 1: The Dark Ages of Computer Architecture

This is the era of domain-specific computing. Or, to use the words of Dave Patterson…

• 8 min read
computer architecture , domain specific computing , moore's law

Whiteboard Wednesdays

Whiteboard Wednesdays - Solving Scan Compression Congestion Issues with Modus 2D…

In this week's Whiteboard Wednesdays video, Rohit Kapur, Distinguished Engineer at…

• less than a min read
Whiteboard Wednesdays , modus , Scan Compression

Breakfast Bytes

Breakfast Buffet for February 2019

https://youtu.be/pNgkoWQE9A4 The three highlighted posts for February were: Who…

• less than a min read
Green Hills , Tensilica , 112g , buffet

Breakfast Bytes

MWC: Voice Enhancement, GPS, Ultrasound, and More

At the recent MWC Barcelona, the conference fka Mobile World Congress, Cadence had…

• 4 min read
alango , nestwave , MWC , Tensilica , sonarax

定制IC芯片设计

Virtuosity: 着色数据是否与MPT流程兼容？

毋庸置疑，兼容的设计能提高公司的业绩和生产效率。任何不兼容的设计都会增加产品的设计周期。 为了便于高阶工艺节点设计中，工程师能创建与多重图形技术（MPT）相兼容的设计流程…

• less than a min read
Chinese blog , ICADVM18.1 , Advanced Node , Multiple Patterning Technology , Virtuoso , Coloring Engine , Custom IC Design , Layout Editing

Verification

And the Winner of the 2019 DVCon U.S. Best Paper Award Is...

Another successful DVCon U.S. 2019 has come and gone, but this year had a particularly…

• 1 min read
DVCon 2019 , paper , Functional Verification , award

Breakfast Bytes

PSA: Americans Will Need Visas for Europe

From 2021, Americans will need a visa for Europe. You read it here first! That means…

• 6 min read
visa , Europe , schengen

Analog/Custom Design

Virtuosity: Reading Vector Files in Virtuoso Visualization and Analysis

Prior to IC6.1.8 and ICADVM18.1, to view digital and analog waveforms along with…

• 2 min read
VCD , Analog Design Environment , ICADVM18.1 , analog , ViVA , Virtuosity , analog stimuli , IC6.1.8 , vector

Breakfast Bytes

Gin and Tonic: The Drink of Barcelona

One thing that is a big deal in Barcelona is gin and tonic, or G&T as it is usually…

• 6 min read
barcelona , MWC

Breakfast Bytes

CDNLive: Travels with a Bear

It's nearly time for the season of CDNLive events, which starts as always in Silicon…

• 5 min read
CDNLive

Analog/Custom Design

Virtuosity: Identifying Those Traces

With the ever-increasing number of simulations required to be run these days, the…

• 3 min read
Explorer , plotting , ADE XL , Virtuoso , Analog Design Environment , ViVA , ADE-XL , Virtuosity , Assembler

Whiteboard Wednesdays

Whiteboard Wednesdays - Diagnostics – What Makes Modus Diagnostics an Industry Leading…

Cadence distinguished engineer Rohit Kapur introduces diagnostic capabilities in…

• less than a min read
Whiteboard Wednesdays , modus

Breakfast Bytes

MWC Part Dos

Yesterday I wrote my first post about MWC19 Barcelona . Today is the continuation…

• 8 min read
5G , MWC , daimler , BMW , ARM

Breakfast Bytes

MWC Barcelona

Last week it was MWC Barcelona. As seems to be the fashion, like with CES, MWC just…

• 7 min read
5G , gsma , MWC , mobile , vodaphone

Breakfast Bytes

Sunday Brunch Video for 4th March 2019

https://youtu.be/wjX4hOvb9-I Made at MWC19 Barcelona (camera JD Estella) Monday…

• less than a min read
Automotive , connx b20 , lidar , mwc19 , radar , MWC , 112g , v2x , SerDes , mobile , bitcoin , Sigrity , ARM , Breakfast Bytes , blockchain

PCB、IC封装：设计与仿真分析

Allegro PCB Editor: 进阶使用技巧

本文将和大家分享Allegro PCB Editor的进阶使用技巧，旨在利用快捷键操作而减少鼠标点击次数，同时包含了定制特定的应用环境，让工具发挥最大效率的方法和示例…

• less than a min read
Chinese blog , 软件技巧 , PCB设计 , 中文 , Allegro PCB Editor , Allegro PCB编辑器 , Allegro

Breakfast Bytes

Who Is Satoshi Nakamoto?

Nobody knows. Really. Here's what is known. He (or maybe it's she or they) is the…

• 8 min read
satoshi nakamoto , cyptography , bitcoin , blockchain
CDNS - Fix Layout Hompage