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The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate
• 7 min read
featured , infrastructure ai , agentic ai , Principled Simulation , physical ai

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About ADW’s Flow Manager? 16.6 Has Many New Enhancements!

The 16.6 Allegro Design Workbench (ADW) Flow Manager has been enhanced to provide…

• 2 min read
PCB , Allegro Design Entry , Allegro 16.6 , cadence , 16.6 , Directive Lockhing , Allegro Design Workbench , Library flow , color , Team design , Library and design data management , SPB , PCB Editor , Design Entry HDL , Layout , design , PCB design , Design Entry , Grzenia , ConceptHDL , library , Schematic , Allegro

Verification

Verification IP: Five More Things I Learned By Browsing Cadence Online Support

After talking about some tips for using trace files in debugging Verification IP…

• 4 min read
Verification IP , NVMe , NVMe PureView VIP Usage , Instantiating VIP models with SystemVerilog , USB , Denali Migration Guide , Integrating USB 3.0 PHY DUT , PHY DUT , Verification Flow USB , PureView USB 3.0 VIP.

Analog/Custom Design

Coming Soon: Asia-Pacific Mixed Signal Summit and Tech-On-Tour Events

Cadence is bringing the Analog/Mixed-Signal Summit to Shenzhen, China, and the Mixed…

• 1 min read
conformal , SystemVerilog , EAD , AMS , EDI , Low Power , IP , Penang , Technology on tour , mixed-signal ToT , Cadence events , tech on tour , AMS Designer , behavioral modeling , Encounter Digital Implemenation , Advanced Node , analog , Incisive , Shenzhen , LDE , analog/mixed-signal , Virtuoso , mixed-signal summit , RNM , mixed signal , SMG , Cadence Community , Singapore , verification

Analog/Custom Design

Virtuosity: 20(!) Things I Learned in June by Browsing Cadence Online Support

Wow! There was an amazing amount of new content added last month. A lot of new videos…

• 2 min read
AMS , Low Power , Virtuoso Space-based Router , VSR , MMSIM , SKILL for the Skilled , Virtuoso , Schematic Editor , Virtuosity , mixed signal , SKILL++ , Virtuoso Layout Suite , SKILL , Schematic

System, PCB, & Package Design 

Customer Support Recommended - Working with NetGroups in Allegro Design Entry CI…

Allegro Design Entry CIS provides a new feature called NetGroup, which offers an…

• 4 min read
PCB , Allegro 16.6 , Allegro Design Entry CIS , NetGroups , PCB design , vectors , buses , Schematic , hierarchical block , scalars , Allegro

System, PCB, & Package Design 

Bending a Few IC Package Design Rules – With Confidence

Somewhere out there is an IC package designer who has been given design guidelines…

• 2 min read
PCB , IC Packaging and SiP Design , SiP , IC Packaging , Allegro Sigrity SI base , IC package design , APD , package design rules , physical layout design , XtractIM , PowerDC , PowerSI

Verification

Cadence Verification IP AppNotes Demonstrate the Use of Trace Files in Debugging

Cadence Verification IP (VIP) provides solutions for verifying compliance and compatibility…

• 4 min read
LFPS , Verification IP , Trace files , Denali to Cadence Migration , debug , PureSpec , VIP , PCIE2.0 , Application Notes , Appnotes , USB3.0 , Low Frequency Periodic Signaling , SuperSpeed USB Inter-Chip , debugging , SSIC

SoC and IP

M-PCIe—The New Big Thing from MIPI Alliance and PCI-SIG

If you’re reading this, you must have heard about the M-PCIe specification that has…

• 3 min read
controller IP , Intel , PCI Developers Conference , Design IP , IP , MIPI Alliance , cadence , Jacek Duda , controller , PHY , MIPI , M-PCIe , Arif Khan , SoC , Warsaw , future of IP , semiconductor IP , SoC Realization , PCI , M-PHY , PCI-SIG , 2013

System, PCB, & Package Design 

What's Good About FSP’s Schematic Generation? 16.6 Has Many New Enhancements!

The 16.6 release of Allegro FPGA System Planner (FSP) has MANY new enhancements in…

• 4 min read
Allegro 16.6 , cadence , FPGA-PCB Co-Design , FPGA System Planner , 16.6 , FPGAs , Design Entry HDL , component browser , symbol , design , Grzenia , Librarians , library , Schematic , FPGA , FPGA: PCB

Verification

How-To AppNotes on Cadence Palladium-XP Help Users Get the Basics Right

In simulation acceleration, there are multiple reasons for using gate-level netlists…

• 3 min read
Acceleration , netlist files , Palladium , LSF , Palladium XP , Emulation , Simulation acceleration , Cadence Application Notes , Compute server , Load Sharing Facility

System, PCB, & Package Design 

What's Good About Capture’s Find Command? 16.6 has a few new enhancements!

The 16.6 release of Alelgro Design Entry CIS (Capture) has added productivity enhancements…

• 1 min read
capture , Cadence Design Systems , Allegro 16.6 , Design Entry CIS , cadence , Find command , OrCAD Capture , 16.6 , Capture CIS , hierarchical schematics , SPB , Find result , design , OrCAD , Design Entry , Grzenia , PCB Capture , Schematic , Allegro

Verification

The Art of Modeling in e

Verification is the art of modeling complex relationships and behaviors. Effective…

• 4 min read
AF , Specman , Incisive , e language , Funcional Verification , coverage driven verification (CDV) , Modeling

Analog/Custom Design

OpenAccess (OA) Based Flow - Efficient Implementation of Mixed-Signal Design for…

I had the great opportunity to represent Cadence at the Design Automation Conference…

• 2 min read
Solutions , DAC , cadence , Analog-Centric , Austin , Open Access , analog , VDI , Digital-Centric , Virtuoso , digital , oa , Encounter Digital Implementation , mixed signal , Texas Instruments , Mixed-Signal Methodology Book

Verification

Rapid Adoption Kit (RAK) -- Creating UVM Verification Environments with Hardware…

The hands-on, learning-by-doing, trying, discovering, failing and learning approach…

• 2 min read
Palladium-XP , RAK , hardware assisted verification , Palladium XP , UVM Acceleration , Simulation acceleration , Cadence Hardware Acceleration , System Level Design Verification , Rapid Adoption Kits , RAKs

SoC and IP

Cadence First to Demo Complete M-PCIe PHY and Controller Solution at MIPI and PCI…

One of the hottest (or should I say coolest – because low power is so important)…

• 3 min read
Intel , PCI Developers Conference , Design IP , IP , Gen3 , cadence , LeCroy , controller , PHY , DevCon , MIPI , M-PCIe , PMC , Arif Khan , PCIe , semiconductor IP , PCI , PCI Express , M-PHY , 2013

Verification

Forte and Cadence at DAC: How to Deploy High-Level Synthesis

It's no secret that the transition to high-level synthesis (HLS) has historically…

• 2 min read
High-Level Synthesis , Mark Warren , DAC , C-to-Silcon Compiler , Mike Meredith , Jack Erickson , Cadence Theater , DAC 2013 , Brett Cline , Forte Cynthesizer , SystemC , HLS , ESL , C/C++

System, PCB, & Package Design 

What's Good About DEHDL’s Hierarchical Split Symbols? The Secret's in the 16.6 Release

The complexity of the designs is constantly increasing and more and more logic is…

• 2 min read
PCB , split symbols , Allegro Design Entry , hierarchy , Allegro 16.6 , cadence , DEHDL , symbol editor , 16.6 , Library flow , hierarchical schematics , Library and design data management , Design Entry HDL , hierarchical split symbols , design , PCB design , Design Entry , Grzenia , Librarians , ConceptHDL , library , Schematic

System, PCB, & Package Design 

Catch, Correct, and Prevent Common Package Design Errors with the 16.6 Cadence APD…

Designing an IC package substrate is a complex task. From picking the right materials…

• 3 min read
stacked dies , SiP , IC Package , IC Packaging , Digital SiP design , 16.6 , IC Packaging and SiP , APD , wirebonds , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , APD 16.6 , SiP Layout , wirebonding , wirebond profile library , IC Package Physical layout and co-design

SoC and IP

MIPI Alliance Meeting Reflects the Rapid Growth of the Mobile Market

Let me start this entry on a bit of a personal note. As a Pole, I was very happy…

• 3 min read
controller IP , Design IP , IP , MIPI Alliance , D-PHY , Jacek Duda , BIF , Slimbus , IP integration , MIPI , CSI , Rick Wietfeldt , USB-IF , DSI , SoC , broadcom , Warsaw , future of IP , Evatronix , Qualcomm , SoC Realization , PCI Express , M-PHY , PCI-SIG
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