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The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate
• 7 min read
featured , infrastructure ai , agentic ai , Principled Simulation , physical ai

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
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Blog - Post List
Latest blogs

Analog/Custom Design

SKILL for the Skilled: Introduction to Classes -- Part 3

In the previous posting Introduction to Classes -- Part 2 we saw the high level…

• 8 min read
Team SKILL , programming , Sudoku , classes , IC 6.1.5 , object orientation , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL

Verification

Too Many Missing Real-World Assertions?

Well, here I am embarking on my fifth post in which I point out illogical situations…

• 4 min read
ABV , Functional Verification , formal , assertions , Assertion-based verification

System, PCB, & Package Design 

Team Allegro to Preview PCB 3D Full-Wave Technology at EPEPS 2011

At the Electrical Performance of Electronic Packaging and Systems conference ( EPEPS…

• 1 min read
PCB , UIUC , EMS2D , EPEPS , interconnects , PCB PI , packaging , 3D extraction , PCB Signal and power integrity , Signal Integrity , full-wave , Allegro PCB SI , PCB design , EM , EMS3D , DDR3 , Allegro

Verification

Formal Verification with Asynchronous Clocks

Many designs have multiple independent clock inputs with different frequency specifications…

• 2 min read
ABV , asssertion-based verification , Joerg Mueller , Verification methodology , Functional Verification , Formal Analysis , formal , SVA , PSL , assertions , IEV , Formal verification , IFV , verification

System, PCB, & Package Design 

What's Good About Allegro GRE Disabling Bundle Compression? It’s in the 16.5 Release

With the SPB16.5 release of Allegro Global Route Environment (GRE) , you can now…

• 1 min read
PCB , PCB Layout and routing , bundle compression , global route , Routing , Allegro 16.5 , PCB Editor , Layout , design , PCB design , SPB16.5 , Allegro PCB Editor , GRE , disabiling bundle compression , Allegro

Verification

Automating UVM to Tackle Insidious HW/SW Bugs

You've just sat through a 2-hour program review. The 30 minutes you spent describing…

• 1 min read
SystemVerilog , uvm , bugs , Duolog , universal verification methodology , Accellera VIP TSC , David Murray , IES

RF Engineering

Guidelines for Maximizing Speed vs Accuracy for Harmonic Balance - Part 1

Greetings, I am often asked for guidelines on maximizing speed vs. accuracy for SpectreRF…

• 2 min read
RF , RF Simulation , analog/RF , APS , HB , Spectre RF , Analog Simulation , Virtuoso Spectre Simulator GXL , ADE , Virtuoso Spectre Simulator XL , spectreRF , RF design , harmonic balance

System, PCB, & Package Design 

What's Good About Allegro PCB Router HDI Via Tangency? Check Out 16.5!

High Density Interconnect (HDI) techniques are increasing in the PCB domain. HDI…

• 1 min read
PCB , blind vias , global route , Routing , layer stacks , High Speed , via tangency , Allegro 16.5 , PCB Editor , High-Density Interconnect , Layout , via , design , miniaturization , PCB design , SPB16.5 , Allegro PCB Editor , buried vias , HDI , microvia , Allegro

Verification

Free Webinar Thursday 10/13 -- Automating Assertion Generation for Simulation, Formal…

Everyone can agree that Assertion-Based Verification (ABV) is a powerful methodology…

• 1 min read
NextOp , Joe Hupcey III , ABV , methodology , interview , Formal Analysis , BugScope , Incisive , webinar , DVcon , assertion synthesis , assertions , IEV , Yuan Lu , Formal verification , IFV , Assertion-based verification , IES-XL

Verification

17M Gates in 8 Months with 2 Designers -- What is Your ROI for Higher-Abstraction…

In their presentation at the recent SystemC Japan conference, Renesas Micro Systems…

• 3 min read
time-to-market , High-Level Synthesis , verification turnaround , TLM , C-to-Silcon , ROI , System-Level Design , SystemC , C-to-Silicon Compiler , productivity

Digital Design

Encounter Quick Tip: Dimming the Display with F12

I remember when I first started working with the Cooper & Chyan Technology (CCT)…

• 1 min read
dimming display , Encounterer Digital Implementation System , highlight , display , encounter , highlighted objects , darken display , quick tip , F12

Analog/Custom Design

Managing ECOs in Mixed Signal Designs

Imagine you are days away from completing the implementation of a fairly complex…

• 3 min read
ECO , Farhat , mixed signal design , CPF , Open Access , Floorplanning , ECOs , mixed-signal ECOs , Mixed-Signal , encounter , Virtuoso , oa , Mixed signal physical implementation

Verification

Amazon’s New Kindles: More Steps Toward the Paperback Computer

While I understand that a new Kindle Fire at $199 MRSP is significantly more than…

• 4 min read
Verification IP , RPP , SaaS , Joe Hupcey III , paperback computer , Cadence VIP portfolio , Kindle , system realization , VIP , EDA360 , EDA , VSP , Palladium XP , tablet , Hosted Design Solutions , Jim Hogan , Rapid Prototyping Platform , Amazon , Steve Leibson , cloud computing

Digital Design

Encounter Quick Tip: Finding Available Cell Masters with dbGet

When you first start using dbGet, many of your queries branch off the "top" keyword…

• 1 min read
dbGet , finding cells , cell masters , filler cells , encounter , Digital Implementation , Encounter Digital Implementation , quick tip

Verification

Technical Tip on How to Use HDL Assertions in e

While assertion callbacks have existed in Specman/e for several years now, several…

• 2 min read
IntelliGen , Specman , Incisive Enterprise Simulator , Incisive , e , SVA , e language , team specman , OOP , assertions , eRM , simulation , AOP , verification , Assertion-based verification

System, PCB, & Package Design 

What's Good About Allegro Database Locking? See for Yourself in 16.5!

Prior to the SPB16.5 release, multiple designers can edit and update the same Allegro…

• 2 min read
PCB , database locking , Allegro 16.5 , SPB , PCB Editor , Layout , design , PCB design , SPB16.5 , Allegro PCB Editor , Allegro

Verification

edaForum: Evolving Devices from “All in One” to “One for All”

This week I had the pleasure to attend and to present at the 11th annual edaForum…

• 7 min read
PCB , IMC , Intel , virtual platforms , edaForum , virtual prototypes , IP integration , System Development Suite , EDA360 , embedded software , Shirrmeister , IC/package co-design , one for all , hardware/software co-development , Power Analysis , System Design & Verification , Frank Schirrmeister , all in one , Eul , power , debugging , System Design and Verification

Verification

Missing Real-World Assertions in Computer-Land

I was reviewing the page view statistics on the Cadence Functional verification…

• 3 min read
uvm , ABV , outlook , Functional Verification , formal , assertions , Assertion-based verification

Verification

Virtual Platform UART Use Number 3: Using gdb to Debug a Software Application

This is the next installment in my series covering the uses of the venerable UART…

• 7 min read
virtual prototoypes , virtual platforms , TLM , GDB , debug , UART , embedded software , software , SystemC , debugging , linux , System Design and Verification
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