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Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
• 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
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Blog - Post List
Latest blogs

Breakfast Bytes

Linley Gwennap: Specialization Spurs Processor Innovation

Every year in the fall, the Linley Group runs their processor conference. There are…

• 5 min read
security , Intel , linley processor conference , AMD , x86 , IoT , Linley , ADAS , ARM , autonomous vehicles , power , Breakfast Bytes

Breakfast Bytes

What’s for Breakfast? Preview October 3rd to 7th (video)

https://youtu.be/dv54rKmMLRo Monday: Options for 5nm. Silicon can only cut…

• less than a min read
60mV/decade , SystemVerilog , DSP , tensilica LX7 , CPF , Cadence videos , TSMC , parsers , Tensilica , training bytes , verific , n10 , 5nm , 10nm , ARM , floating point , VHDL , IEDM

Whiteboard Wednesdays

Whiteboard Wednesdays - Why Is More Floating-Point Computation Required by DSP Applications…

Why is more floating-point computation required by DSP applications? More and more…

• less than a min read
floating-point , DSP , Whiteboard Wednesdays , IP , communications processing , vision processing , Tensilica , wearables processing , floating point

Breakfast Bytes

Memories Are Made of This: Preview of MemCon

This year's MemCon is on October 11, at the Santa Clara Convention Center. Last year…

• 5 min read
vertical flash , Memory , LPDDR4 , MemCon , Micron , flash , NAND flash , Denali Party , DRAM , memcon 2016 , Breakfast Bytes

SoC and IP

3 Things You Didn't Know About MemCon 2016

Memcon is an event like few others, where SoC architects congregate to learn and…

• 1 min read
DDR4 , LPDDR4 , MemCon , DDR IP

Breakfast Bytes

TSMC: Technology Update

Twice a year TSMC has a big meeting in San Jose. These are the times that there is…

• 7 min read
OIP , 3D packagin , HPC28 , CoWoS , IoT , 28nm , 20nm , 40ULP , fabless , TSMC , ULP , process roadmap , 55ULP , 16ff , 16nm , InFO , 16FFC , n7 , FinFET , n10 , 7nm , 10nm , foundry

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? New Enhanced Backdrill Capability (Reason 4 of…

Adventures in Backdrilling For the past 15 years or so, routing high-speed interfaces…

• 4 min read
backdrill , Allegro 17.2 , PCB design , Allegro PCB Editor , Why Move Up to 17.2

Breakfast Bytes

System Design Enablement with Cadence and TSMC

System-on-chip (SoC) designers are always optimizing what has become known as PPA…

• 3 min read
Low Power , bvp.system-ppa , virtual platform , TSMC , Tensilica , power , Breakfast Bytes

Verification

Back in the Saddle Again

Nearly five years ago, I signed off with my last blog post in the Cadence Community…

• 3 min read
pswg , Perspec , System Design and Verification , System simulation and analysis , Accellera , portable stimulus , System Design and Verification , verification

Breakfast Bytes

Mellanox: Using Palladium ICA Mode

At CDNLive Israel, Yaron Netanel of Mellanox talked about his experience with Palladium…

• 3 min read
Yaron Netanel , CDNLive , debug , mellanox , Palladium , in-circuit acceleration , ICA , cdnlive israel , Breakfast Bytes

Breakfast Bytes

What’s for Breakfast? Preview September 26th to 30th (video)

https://youtu.be/1le_bd4o01Q Monday: System Design Enablement with Cadence and…

• less than a min read
OIP , Memory , MemCon , LPDDR , liinley , SDE , TSMC , antiportfolio , DDR , system design enablement , bessemer ventures , power , microprocessor

Breakfast Bytes

How to Connect Sensors with I3C

A couple of sessions at MIPI DevCon last week were on I3C. This is a new generation…

• 6 min read
MIPI , i2c , sensors , mobile , I3C

Analog/Custom Design

Virtuoso Video Diary: SKILL IDE Performance Analysis Tools

As a SKILL code developer, do you spend a major chunk of your time in fine-tuning…

• 2 min read
Team SKILL , programming , Virtuoso Video Diary , software development , SKILL IDE , Custom IC Design , SKILL++ , Virtuoso Layout Suite , SKILL

Breakfast Bytes

שלום from CDNLive Israel

Shalom. Today is CDNLive Israel in Tel Aviv. At least getting here from San Francisco…

• 5 min read
CDNLive , Lip-Bu Tan , cdnlive israel , perlmutter

Whiteboard Wednesdays

Whiteboard Wednesdays - Evolution of the PCIe Standard

In this week's Whiteboard Wednesdays video, Lana Chan explores the history of PCI…

• less than a min read
Whiteboard Wednesdays , PCIe , PCI Express

Breakfast Bytes

MIPI: Not Just Mobile Any More

On September 14 and 15, MIPI held its first developer conference. For more background…

• 3 min read
5G , Automotive , 4G , CSI-2 , Standards , MIPI , mipi devcon , ADAS , I3C , Breakfast Bytes

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? New Padstack Editor – More Than Just a New GUI…

Customer inputs are key to product improvements I can read your minds as you…

• 5 min read
backdrill , Allegro 17.2 , keepouts , masks , padstack , PCB design , Why Move Up to 17.2 , Allegro

Breakfast Bytes

Signal and Power Integrity Masterclass

At CDNLive Boston, I moderated a panel session on signal and power integrity with…

• 9 min read
DDR4 , CDNLive , dc-dc converters , IBM , Cisco , Oracle , cdnlive boston , advanced bus analysis , Qualcomm , compliance methodology

Academic Network

Cadence at the VLSI Design/CAD 2016 Symposium

Great Academic Networking in Taiwan With the support of the Cadence Academic Network…

• less than a min read
VLSI , Cadence Academic Network
CDNS - Fix Layout Hompage