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Analog/Custom Design

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Data Center

Innovation in Data Center Design and Operations: Highlights from Thésée Event

The Thésée event brought together key partners like France Télévisions, Thésée, Cadence…

Veena Parthan
• 5 min read
featured , Thésée Event , data center , Cadence Reality Digital Twin Platform

Corporate News

Don’t Miss the 2025 North America Open Meeting!

Join Visionaries, Discover Breakthrough Tech, and Power Your Next Big Idea Are you…

Corporate
• 1 min read
featured , innovation , Beta CAE , event , AI

Corporate News

Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130
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Blog - Post List

Latest blogs

Digital Design

Five-Minute Tutorial: Where To Find More Encounter Digital Implementation (EDI) System…

We've had some people joining the forum lately that are either brand-new to Encounter…

• 1 min read
video , tutorial , beginner , training , EDI 10.1 , Digital Implementation , init_design , five minute tutorial , EDI 11 , mmmc

System, PCB, & Package Design 

What's Good About Allegro DFM/DRC Updates? 16.5 Has a Few New Enhancements!

Allegro PCB Editor has been enhanced in the 16.5 release with three (3) additional…

• 3 min read
PCB , PCB Layout and routing , DFA , backdrill , DRC , ADRC , Allegro 16.5 , SPB , PCB Editor , Layout , assembly DRCs , backdriling , design , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , Allegro

Analog/Custom Design

Virtuoso AMS Designer Wins the China ACE Best EDA Product Award

The China Annual Creativity in Electronics (ACE) Awards was established to recognize…

• less than a min read
AMS , Virtuoso-AMS , China , mixed signal design , ACE award , AMS-Designer , AMS Designer , Mixed-Signal , wreal

Digital Design

Five-Minute Tutorial: Default Naming Conventions in Encounter Digital Implementation…

This is a topic that frequently comes up on both internal and external forums. And…

• 2 min read
EDI , naming , timing debug , tutorial , encounter , Digital Implementation , Encounter Digital Implementation , default naming conventions , five-minute

System, PCB, & Package Design 

Altera 28 Gbps Stratix V IBIS-AMI Models Now Blazing Channels with Allegro PCB S…

Altera and Cadence recently collaborated and completed correlation work with Allegro…

• 2 min read
PCB SI , PCB , Stratix V , Multi-Gigabit , Altera , IBIS , model kit , PCB power integrity , FPGAs , IBIS-AMI , Signal Integrity , PCB design , channel analysis , SI analysis and modeling , FPGA , Allegro

Verification

Virtual Divide and Conquer Enables Fixed Sub-Systems

The 17th North American SystemC User Group meeting ( NASCUG ), will take place this…

• 3 min read
IP , zynq , virtual platforms , TLM , platform , virtual prototypes , fixed sub-systems , sub-systems , Tensilica , subsystems , OMAP , DVcon , SystemC , xilinx , NASCUG , FPGA , System Design and Verification , verification

Verification

Gentlemen, Start Your Simulation Engines

As we outlined in our recent performance white paper , every verification team has…

• less than a min read
performance , SystemVerilog , Multi-Core , Incisive , Funcional Verification , Incisive Enterprise Simulator (IES) , IES , IES-XL

System, PCB, & Package Design 

What’s Good about OrCAD Apps? Symbol and Footprint Creation Just Got a Lot Easier…

Creating the symbols and footprints necessary to complete your designs can be a difficult…

• 2 min read
PCB , Marketplace , OrCAD Capture Marketplace , Footprint , OrCAD Capture , Capture CIS , Capture-CIS , OrCAD online store , Library flow , Allegro 16.5 , Library and design data management , SPB , webinar , symbol , OrCADapps , "PCB design" , OrCAD , PCB design , Design Entry , SPB16.5 , Librarians , library , PCB Capture , Schematic , Allegro

System, PCB, & Package Design 

What's Good About Capture’s Placement Report? Look to SPB16.5 and See!

The 16.5 release of OrCAD Capture includes the ability to generate a report with…

• less than a min read
"capture CIS" , Allegro Design Entry , hierarchy , Design Entry CIS , flat schematics , Capture CIS , Capture-CIS , property , hierarchical schematics , Allegro 16.5 , SPB , placement report , design , OrCAD , 16.5 , Design Entry , SPB16.5 , PCB Capture , Schematic , Allegro

Verification

Using a Linaro File System on the Cadence Virtual Platform for the Xilinx Zynq-7000…

Linaro has emerged as a great place to find well tested toolchains, Linux kernels…

• 3 min read

Verification

DVCon 2012 Preview: Focus on Formal & ABV Events and Papers

In a few short weeks DVCon 2012 will be upon us ( Feb. 27 - March 1 in San Jose …

• 2 min read
Joe Hupcey III , ABV , verification strategy , Functional Verification , Formal Analysis , ABVIP , Bin Ju , video , tutorial , Facebook , Chris Komar , DVcon , apps , assertion synthesis , assertions , robot , IEV , Assertion-Driven Simulation , Darrow Chu , Formal verification , IFV , Assertion-based verification

System, PCB, & Package Design 

What's Good About ADW’s Server Metrics? Check out the 16.5 Release and See!

The Allegro Design Workbench (ADW) 16.5 has the capability of providing usage metrics…

• 1 min read
PCB , data management , usage metrics , Allegro Design Workbench , Library flow , server metrics , Team design , Allegro 16.5 , SPB , LRM , design data management , configuration manager , design , Library Revision Manager , PCB design , SPB16.5 , metrics , library , ADW

Analog/Custom Design

SKILL for the Skilled: Introduction to Classes -- Part 5

In the previous SKILL for the Skilled postings, we looked at a pretty good algorithm…

• 4 min read
Team SKILL , programming , Sudoku , object orientation , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL

Analog/Custom Design

Things You Didn't Know About Virtuoso: Measurements Across Corners

In Virtuoso IC 6.1.5 ISR6, we released a new feature in ADE XL, which had been requested…

• 1 min read
Corners , Virtuoso IC6.1.5 , custom/analog , IC 6.1 , Corners analysis , IC615 , IC 6.1.5 , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , ADE-XL , Custom IC Design

Digital Design

Five-Minute Tutorial: Change The Background Color Of EDI

Today's tutorial could probably be called a One-Minute Tutorial, since it's so quick…

• 1 min read
EDI , changing color , color , encounter , Digital Implementation , five minute tutorial , background color

Verification

The Zynq Virtual Platform: Not Just for Pre-Silicon

One of the biggest misconceptions about Virtual Platforms is that they are only useful…

• 4 min read
Virtual System Platform , zynq , virtual platforms , Zynq-7000' , pre-silicon , virtual prototypes , post-silicon , embedded software , Watchdog Timer , SystemC , linux

System, PCB, & Package Design 

What's Good About Property Changes in DEHDL? The Secret's in the 16.5 Release!

In the 16.5 release, all connectivity changes are stored in the hierarchical block…

• 11 min read
PCB , Allegro Design Entry , hierarchy , electrical constraints , flat schematics , uprev , hierarchical schematics , property changes , Allegro 16.5 , Constraint Manager , Design Entry HDL , design , Design Entry , SPB16.5 , ConceptHDL , Schematic , Allegro

System, PCB, & Package Design 

What's Good About PCB SI Signal Integrity Application Mode? It’s in the 16.5 Release

In release 16.0, the concept of Application Modes was introduced. These application…

• 2 min read
PCB SI , PCB , PCB Layout and routing , SI , application mode , High Speed , Allegro 16.5 , Layout , Signal Integrity , PCB Signal integrity , PCB design , 16.5 , Allegro

Verification

System-Level Design and the Waves of EDA

Before January comes to an end it is time for my annual flashback and brief reflection…

• 5 min read
virtual prototypes , IP integration , abstraction , VCC , VSI , IP assembly , cars , EDAC , software , automobiles , 1997 , Virtual Platforms , IEEE Spectrum , Schirrmeister , ESL , ESL system-level design
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