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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

Verification

From Cadence Earning Call This Week

In system development, we have focused on two key customer challenges. First…

• 1 min read
TLM , NVIDIA , ITRI , Silicon Hive , System Design and Verification , OVM , Nethra Imaging , Rhode , Schwartz

Verification

Improve Productivity Through Communication and Learning

I regularly spend time talking to people about the importance of the connection between…

• 5 min read
System Design and Verification , CDNLive! 2009 Silicon Valley , Virtual Platforms , ISX

Verification

OVM Tricks and Treats

Your kids may be going house to house for treats, but you can get a big OVM sugar…

• 2 min read
SystemVerilog , OVM ML , Functional Verification , OVM , OVM e , OVM SV , e , AMIQ , IES , OVM SC

Verification

Why Verification Engineers Are Like Football Players

Is it their raw power? Is it the cheerleaders? Why are verification engineers like…

• less than a min read
performance , CDNLive , Functional Verification , OVM , Multi-Core , MDV , IES , IES-XL

Digital Design

Encounter How-To: Write Text to The Log File With "Puts"

Here's a simple but useful tip that shows how to write to the log file using the…

• 1 min read
EDI system , Digital Implementation , Encounter Digital Implementation , tcl

System, PCB, & Package Design 

What's Good About Net Color Override in Allegro? Check Out The SPB16.2 Release and…

Color assignment in Allegro PCB Editor has been accomplished with either a class…

• 1 min read
SPB 16.2 , color , Allegroro , PCB design

Verification

4 Minute Demo: OVM e Compliance Checks Added to AMIQ's DVT

Specmaniacs rejoice: long time Verification Alliance partner AMIQ has just added…

• less than a min read
eclipse , Specman , Functional Verification , OVM , OVM e , e , AMIQ

Verification

Where’s The “You” In The OVM?

Cadence and Mentor have dedicated teams to the development and support of the OVM…

• 2 min read
OVM ML , Functional Verification , OVM , OVM e , OVM SV , OVM Advisory Group , OVMWorld , IES-XL

Verification

4G Is Here Now

If you have not heard about 4G yet, it is here now. Verizon has already paid earlier…

• less than a min read
4G , System Design and Verification , Verizon , Rohde & Schwarz , Wimax , mobile

Analog/Custom Design

Things You Didn't Know About Virtuoso: ViVA

Sorry I've been missing from this space for so long. I've been busily working on…

• 3 min read
ViVa-XL , IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

Verification

Keeping Trident Missiles "On Target" With System-Level Verification

Can you think of a more critical application for system-level verification than making…

• 1 min read
Mil-Aero , TLM , Draper Labs , System Design and Verification , Palladium

Digital Design

How To: Purge Interactive Constraints in MMMC Mode

These tips are applicable to the Encounter Digital Implementation System . Back in…

• 3 min read
timing constraints , Digital Implementation , mmmc , Encounter Digital Implementation System 8.1 , tcl

Verification

Specman/IES-XL 9.2 Is Posted - Come And Get It!

We interrupt the Specman 9.2 preview series and ClubT news to announce that 9.2 is…

• less than a min read
Specman , CDNLive , Functional Verification , e , Incisive Seminar , ClubT , Incisive Enterprise Simulator (IES) , IES-XL

Verification

Why OVM? John Aynsley of Doulos Has 10 Reasons

Believe it or not, sometimes a marketing guy just needs to say less. It's true. It…

• less than a min read
SystemVerilog , OVM ML , Functional Verification , OVM e , OVM SV , SystemC , eRM , OVM 2.0 , OVM SC , IES-XL

System, PCB, & Package Design 

What's Good About Package Power Integrity? You'll Need SPB16.2 To See!

As clock and data frequencies increase and high-speed systems become ever more densely…

• 10 min read
SPB 16.2 , SiP , Integrity , Allegroro , PCB design , power , PaKSi

Verification

Demo: New Signal Tracing Capability in Incisive Enterprise Simulator

One of the great things about working here at Cadence is having the opportunity to…

• less than a min read
Functional Verification , simvision , Incisive , Incisive Enterprise Simulator (IES) , IES , verification , IES-XL

Verification

Extending Multiple When-Subtypes Simultaneously

[For those of you that didn't / can't make it to a ClubT last week/this week , here…

• 4 min read
Specman , Functional Verification , e , ClubT , macros , AOP , IES-XL

Verification

Synopsys’ “Synphony” Announcement – Welcome to the Party!

I’m glad Synopsys realized the world really IS moving to the next higher level of…

• 1 min read
TLM , RTL , System Design and Verification , ESL , verification

Verification

Incisive Enterprise Verifier for Everyone!

Last week Cadence announced a new product called Incisive Enterprise Verifier (IEV…

• 2 min read
verifier , Functional Verification , formal , OVM , Incisive , IEV
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