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Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement
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Blog - Post List

Latest blogs

Analog/Custom Design

Virtuosity: 10 Things I Learned in December By Browsing Cadence Online Support

In addition to the R&D engineers who actually develop our software, the folks in…

• 4 min read
Variability Aware Design , AMS , Analog Design Environment , Virtuoso IC6.1.5 , Virtuoso Space-based Router , VSR , Analog Simulation , Cadence Space-based Router , workshop , IC615 , IC 6.1.5 , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , Analog Design Environment , Schematic Editor , ViVA , ADE-XL , mixed signal , Custom IC Design , Virtuoso Layout Suite

Analog/Custom Design

Library "Safe Margins" -- Are They Really Saving Your Design?

Designers need to radically re-think their strategies for timing closure to get the…

• 4 min read
Standard Cell , memory characterization , Process Variation , Elzeftaki , library characterization , Timing Closure , Complex IO , PVT corners , safe margins , Complex Cell

Analog/Custom Design

SKILL for the Skilled: Part 6, Many Ways to Sum a List

In a previous post I presented sumlist_2b as a function that would sum lists of length…

• 5 min read
Team SKILL , programming , Jim Newton , sum a list , IC615 , SKILL for the Skilled , summing , Lisp , SKILL++ , SKILL

System, PCB, & Package Design 

Customer Support Recommended – Pin Swapping in Allegro Design Entry CIS and PCB …

Placement and routing have always been an integral part of printed circuit board…

• 4 min read
capture , "capture CIS" , SPB16.3 , Allegro Design Entry , Allegro 16.6 , customer support , PCB design" , net swap , Design Entry CIS , OrCAD Capture Marketplace , Routing , OrCAD Capture , 16.6 , Allegro 16.3 , SPB 16.3 , Capture CIS , Capture-CIS , Allegro 16.5 , Allegro 16.2 , SPB16.2 , Appnote , pinswap , "PCB design" , OrCAD , swap , 16.5 , Design Entry , SPB16.5 , Allegro PCB Editor , pin swap , application note , OrCAD PCB Editor , library , PCB Capture , Schematic

Analog/Custom Design

Revamped Mixed-Signal Solutions Portal Reflects Cadence Leadership and Commitmen…

Cadence holds a leading position in the EDA industry due to its broad product portfolio…

• 1 min read
CDNLive , cadence , AMS Designer , custom , Design Challenges , analog , web page , Mixed-Signal Methodology Guide , Mixed-Signal , Mixed-signal solutions web page , Virtuoso , mixed-signal book , digital , implementation , mixed signal , Encounter Digital Platform , web site , verification

Verification

Specman: Determining a Good Value for optimal_process_size

Specman's Automatic GC Settings mechanism is aimed at eliminating the need for users…

• 7 min read
AF , memory usage , optimal_process_size , Specman , garbage collection , Functional Verification' signal integrity , e language , optimal process size , memory consumption , OPS

Verification

System Design 2012 – Real Users Achieving Real Results!

This morning the final success story my team has been working on for this year went…

• 4 min read
ESL Market , Nufront , Altair , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , cadence , Sigma , Acceleration , Functional Verification , LeCroy , Dynamic Power Analysis , Doulog , System Design and Verification , Freescale , Methods2Business , System Development Suite , Samsung , embedded software , Rohde & Schwarz , Ericsson , LSI , Palladium XP , Emulation , CSR , CDNLive! , ST Microelectronics , Texas Instruments , xilinx , DAC 2012 , ARM , Schirrmeister , Accelerated Verification IP , low power optimization

RF Engineering

Simulating Crystal Oscillators is Much Easier in MMSIM12.1 - Part 2

Greetings, Simulating crystal oscillators got a lot easier in MMSIM12.1... We…

• 5 min read
RF , RF Simulation , analog/RF , APS , Circuit simulation , Virtuoso Spectre , HB , Spectre RF , Analog Simulation , MMSIM , Virtuoso Spectre Simulator GXL , MMSIM 12.1 , analog , Analysis , ADE , Virtuoso Spectre Simulator XL , spectreRF , Spectre , RF design , Circuit Design , VCO , crystal oscillator , Oscillator , simulation

System, PCB, & Package Design 

Be Among the First IC Packagers to Experience the New GDS-II Stream Interface in…

For most IC package designers, the GDSII format is a part of daily life. You may…

• 5 min read
SiP , IC Package , IC Packaging , GDSII , packaging , cadence , Digital SiP design , stream , 16.6 , GDS-II , IC Packaging and SiP , APD , IC Packaging & SiP design , Allegro Package Designer , APD 16.6 , SiP Layout , Physical layout and co-design

RF Engineering

Simulating Crystal Oscillators is Much Easier in MMSIM12.1 - Part 1

Greetings! Simulating Crystal Oscillators got a lot easier in MMSIM12.1... We…

• 8 min read
RF , RF Simulation , analog/RF , 12.1 , HB , Spectre RF , ADE-L , Analog Simulation , MMSIM , MMSIM 12.1 , analog , RF spectre spectreRF , Virtuoso Spectre Simulator XL , spectreRF , RF design , Circuit Design , harmonic balance , VCO , crystal oscillator , Oscillator

Verification

University of Aizu and Cadence Collaborate to Deliver a Course Featuring High-Level…

Today we issued a Japan-only press release announcing a high-level synthesis joint…

• 2 min read
High-Level Synthesis , university , TLM-driven design , TLM , japan , SystemC , C-to-Silicon Compiler , DAC 2012 , Aizu , C++

Verification

C-to-Silicon 12.2 Available for Your Holiday Shopping List

The winter holiday season is that special time of year when we get bombarded with…

• 4 min read
High-Level Synthesis , Flex Channels , C-to-Silicon 12.2 , Jack Erickson , IP re-use , rtl compiler , SystemC , C-to-Silicon Compiler , HLS , clock gating , QoR , System Design and Verification

Analog/Custom Design

Mixed Signal Technology Summit Proceedings Now Available

In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California…

• 5 min read
Static timing analysis , mixed-signal seminars , AMS , static analysis , EDI , microcontrollers , ARM Cortex M0 , mixed signal design , cadence , Functional Verification , mixed signal methodology , mixed signal solution , Open Access , STA , Verilog-AMS , timing model , FTM , Mixed-Signal , MCUs , encounter , Mixed-Signal Technology Summit , analog behavoral , analog behavioral models , analog/mixed-signal , mixed signal physical implementation open access , model validation , Signal Integrity , Virtuoso , Spectre , Cortex-M0 , oa , RNM , mixed signal methodology guide , real number types , Mixed signal physical implementation , behavioral models , mixed signal , OA: OpenAccess , cortex M , mixed-signal design , wreal , real number models , ARM , ARM-Cortex-M , OpenAccess , SPICE , mixed signal implementation , liberty model , simulation , AMS Verification

Verification

Securing the Internet of Things

While I had looked at the challenges of hardware/software integration in various…

• 3 min read
security , Intel , device security , hackers , System Development Suite , Amphion Forum , embedded software , Green Hills , burning printer , Mocana , software security , cyber attacks , Internet of Things , phone emissions , Schirrmeister , HW/SW Co-Development

System, PCB, & Package Design 

What's Good About RF PCB and Layout? 16.6 Has Many New Enhancements!

The 16.6 Allegro RF PCB application has many new enhancements. I’ll cover a few over…

• 3 min read
PCB , PCB Layout and routing , RF , Allegro 16.6 , RF PCB , Routing , 16.6 routing , PCB Editor , Layout , design , "PCB design" , PCB design , Grzenia , Allegro PCB Editor , Allegro

Verification

Avoid Overly Long Expressions in Specman e Code

When you write your e code, a good practice is to avoid expressions that are "overly…

• 3 min read
AF , parsing , Specman , Functional Verification , long expressions , e code , e language

Digital Design

SPICE Correlation Made Easy by Encounter Timing System (ETS)

Hello, and welcome to my first blog! As an application engineer in customer support…

• 4 min read
app note , Static timing analysis , ets , mukesh , STA , spice correlation , Spectre , signoff , ETS create_spice_deck , Encounter Timing System , SPICE

Verification

Update to the Linux Kernel Message System

A few months ago I wrote an Introduction to the Linux Kernel Message System . As…

• 1 min read
Virtual System Platform , virtual platforms , GDB , VAP , cadence , ring buffer , uncompressing Linux , virtual prototypes , System Design and Verification , kernel message system , booting Linux , embedded software , VSP , Imperas , software development , Zynq virtual platform , linux , Zynq-7000 , Embedded Linux , ESL , kernel messaging system , Andrews

System, PCB, & Package Design 

Leverage System Planning to Maximize Performance of Silicon Interposer

Recently, an article was published in Chip Scale Review by Cadence product manager…

• 2 min read
SI , PI , Chip Scale Review , SiP , IC Packaging , Team Allegro , 3D IC , Kevin Rinebold , 3D-IC , Power Integrity , TSV , silicon interposer , Signal Integrity , 2.5D IC , system planning , system co-analysis , 2.5D
CDNS - Fix Layout Hompage