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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
cdns - all_blogs_categories

Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About OrCAD Capture’s Signal Integrity Flow? The Secret's in the 16.6…

With the 16.6 release, you now have the capability of utilizing the PCB SI tools…

• 1 min read
PCB SI , capture , Constraint-driven PCB Design flow , constraint databases , Allegro 16.6 , Design Entry CIS , Signal Intregrity , 16.6 routing , electrical constraints , IBIS , SigXP UI , OrCAD Capture , 16.6 , PCB Signal and power integrity , Capture CIS , Capture-CIS , High Speed , Constraint Manager , Layout , Signal Integrity , OrCAD , OrCAD PCB SI , PCB Signal integrity , Allegro PCB SI , Constraints , Grzenia , SI analysis and modeling , PCB Capture , Schematic , Allegro

Analog/Custom Design

Virtuosity: 10 Things I Learned In January By Browsing Cadence Online Support

This month's highlighted content includes helpful information on wreal modeling,…

• 2 min read
Virtuoso Space-based Router , Rapid Adoption Kit , encounter , calibration , Virtuoso , Analog Design Environment , ADE-XL , AMS simulation , mixed signal , interoperability , wreal , Custom IC Design

Verification

Why C-to-Silicon Compiler HLS has Supported IEEE 1666-2011 SystemC All Along

Recently one of our competitors issued a press release claiming to be the first high…

• 1 min read
asynchronous reset , IEEE 1666-2011 , Incisive , SystemC , C-to-Silicon Compiler , QoR

Verification

IBM and Cadence Collaboration Improves Verification Productivity

Technology leaders like IBM continuously seek opportunities to improve productivity…

• 2 min read
SystemVerilog , uvm , collaboration , IEEE 1800 , Metric Driven Verification , IBM , simvision , OVM , Tom Cole , Incisive , Mixed-Signal , Acellera VIP TSC , MDV , IEV , IES , vManager , IFV , IES-XL

Analog/Custom Design

Things You Didn't Know About Virtuoso: Drag and Drop

I love it when I'm sitting in a meeting with my colleagues or with a group of customers…

• 2 min read
Analog Design Environment , ViVa-XL , Virtuoso IC6.1.5 , IC 6.1 , VIrtuoso drag and drop , IC 6.1.5 , ADE , Virtuoso , ViVA , ADE-XL , drag and drop , Custom IC Design

System, PCB, & Package Design 

What's Good About ADW’s Configuration Manager? Look to 16.6 and See!

The 16.6 Allegro Design Workbench (ADW) Configuration Manager has been enhanced!…

• 1 min read
Allegro 16.6 , 16.6 , Allegro Design Workbench , Library flow , Library and design data management , SPB , design data management , design , PCB design , Grzenia , Librarians , library

System, PCB, & Package Design 

Allegro Sigrity Makes its Debut at DesignCon 2013

After Cadence acquired Sigrity in July 2012, we heard many of the same questions…

• 2 min read
PCB , SI , PI , IC Packaging , SiP Design , Griffin , Designcon 2013 , Power Integrity , Signal Integrity , EDACafe , Sigrity , Allegro PCB Editor , SI analysis and modeling , Allegro Sigrity

Digital Design

Quick Reference - 8 Ways to Optimize Power Using Encounter Digital Implementation…

Everyone knows that the increasing speed and complexity of today's designs implies…

• 4 min read
EDI , EDI system , Vt partition , low power tips , leakage , Jaiswal , EDI 11.1 , 8 ways , encounter digital implementation system , Encounter Digital Implementation , optLeakagePower , Leakage Optimization , power optimization , EDI 11 , dynamic power

Verification

Using the ‘restore -append_logs' Feature

As described in Specman Advanced Option appnote , Specman Elite supports dynamic…

• 3 min read
AF , Specman , debug , Functional Verification , restore append , reseeding , log files , e language , specman elite , restore , restore-append_logs , SAO , dynamic load , simulation

Verification

DVCon 2013 for Formal and ABV Users

At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects…

• 3 min read
Incisive Formal Verifier , Joe Hupcey III , ABV , Joerg Mueller , metric driven verification (MDV) , Functional Verification , Formal Analysis , NVIDIA , ABVIP , formal , formal apps , Vigyan Singhal , Incisive , Incisive Enterprise Verifier , Mike Stellfox , Chris Komar , Oski Technology , DVcon , assertions , formal scoreboard , MDV , IEV , Oski , Formal verification , IFV , Assertion-based verification

Verification

DVCon 2013 for the Specmaniac

At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects…

• 3 min read
Specman , Specman/e , methodology , verification strategy , metric driven verification (MDV) , debug , Functional Verification , Formal Analysis , formal , Incisive Debug Analyzer , e , e language , Mike Stellfox , DVcon , Aspect Oriented Programming , simulation , AOP , verification

System, PCB, & Package Design 

Ease Your IC Packaging Documentation and Manufacturing Exports for Stacked Dies in…

Following our last posting concerning intelligent documentation text, this week we…

• 2 min read
documentation , stacked dies , package , SiP , IC Package , IC Packaging , packaging , cadence , manufacturing exports , Digital SiP design , 16.6 , IC Packaging and SiP , APD , wirebonds , IC Packaging & SiP design , SPB , Allegro Package Designer , IC packaging documentation , SiP Layout , wirebonding , Physical layout and co-design , wirebond profile library , cavity

Verification

Improve Debug Productivity - SimVision Video Series on YouTube

Most verification customers claim that they are spending over 50% of their verification…

• less than a min read
SystemVerilog , Low Power , : Functional Verification , transaction , watch window , metric driven verification (MDV) , cadence , debug , Functional Verification , Debug Performance , UVM-MS , RTL , simvision , Incisive Enterprise Simulator , SimVision watch window , EDA360 , Coverage-Driven Verification , Mixed Signal Verification , Incisive , Verilog , bug , sequences , RTL design , video tutorial , IEV , Incisive Enterprise Simulator (IES) , VHDL , debugging , IES , IFV , IES-XL

System, PCB, & Package Design 

What's Good About FSP Planning Mode? Check Out 16.6!

The Allegro FPGA System Planner (FSP) 16.6 release offers major improvements in Auto…

• 1 min read
PCB , PCB Layout and routing , Allegro 16.6 , net swap , Routing , FPGA-PCB Co-Design , FPGA System Planner , Placement Edit , FPGAs , PCB Editor , Front-end PCB design , design , FSP , pinswap , swap , PCB design , Design Entry , Grzenia , pin swap , FPGA , FPGA: PCB

Analog/Custom Design

Introduction to Cadence Virtuoso Advanced Node Design Environment

What can designers do about advanced node technology? This is an introduction to…

• 6 min read
STI , Virtuoso Advanced Node , length of diffusion , custom/analog , Routing , analog prototyping , Double Patterning , layout-dependent effects , Ishikawa , custom , odd-loop marker , 20nm , Advanced Node , module generation , analog , WPE , design flow , LDE , dynamic coloring , LOD , well proximity , Placement , stress , interconnect layers , Custom IC Design , local interconnect

Verification

A Concrete Linux Virtual Platform Example

Virtual platforms are used to find many different types of system and software issues…

• 3 min read
Device Drivers , zynq , virtual platforms , virtual prototypes , UART , embedded software , Ubuntu , softtware bugs , SystemC , xilinx , Zynq virtual platform , debugging software , linux , Jason Andrews , Zynq-7000 , System Design and Verification

Verification

A 10-year Look-Back from 2013 – Some Technology Predictions that are Coming True…

It is January 2013, the year has begun and it is time for my annual 10 year look…

• 4 min read
SystemVerilog , Apple , Low Power , integration , Google Glass , virtual platforms , tungsten , GPS , Cell Phone , base stations , MP3 , virtual prototypes , IBM , Harry Goldstein , PDA , abstraction , google , Linda Geppert , 10 year , Palm , hardware/software CoDesign , 10 year look-back , software , IEEE Spectrum , Mark. E. Dean , Schirrmeister , ESL , iPhone , ESL system-level design

System, PCB, & Package Design 

What's Good About DEHDL’s Interface Aware Design? The Secret's in the 16.6 Release

Components in a design communicate with each other based on some rules or protocols…

• 3 min read
interface aware design , PCB , PCB Layout and routing , constraints manager , Allegro 16.6 , DEHDL , signal grouping , hierarchical net groups , 16.6 , interface definitions , interfaces , PCB Editor , Design Entry HDL , PCB design , Grzenia , net groups , Allegro

Verification

Specman: An Assumed Generation Issue and its Real Root Cause

Random generation is always a complex task, and differences in results are usually…

• 2 min read
AF , IntelliGen , Specman , debug , Functional Verification , garbage collection , lists , Incisive , e code , Generation , e language , assumed generation , Funcional Verification , Zander , vManager , random generation
CDNS - Fix Layout Hompage