Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

Miniaturization Through Embedding Packaged Components – Part2

This blog was written by a guest blogger – Mark Beesley of AT&S. His company is…

• 2 min read
embedded components , AT&S , embedded die in laminate , ECP , TeamAllegro , PCB Editor , miniaturization , Beesley , "PCB design" , SPB16.5 , Allegro PCB Editor , microvia , Allegro

Verification

Pre-RTL Software Development -- You Can't Get Your Product to Market Without It!

It's been an exciting month for the System Realization team with the announcement…

• 2 min read
Virtual System Platform , TLM 2.0 , virtual prototype

Verification

Blazing a Trail With Ubuntu

One of the most popular blogs I wrote is running Incisive on Ubuntu . I have had…

• 3 min read
SystemC debugging , Virtual System Platform , debug , Ubuntu , SystemC , debugging , linux , System Design and Verification

Analog/Custom Design

CPF Low Power Simulation with Analog and Mixed-Signal Design (CPF-AMS)

We have been talking about low power simulation and the Common Power Format (CPF…

• 2 min read
Low Power , CPF , Verilog-AMS , analog , Mixed-Signal , Spectre , Connect Module , mixed signal , wreal , SPICE

Verification

A Look at the Ongoing Functional Verification Seminar Series

Being a Marketing guy, one thing that I really enjoy is getting on the road for…

• 2 min read
Functional Verification , formal , Incisive , Mixed-Signal , metric-driven verification , MDV , IEV , IFV

Digital Design

Tab Completion with Encounter's dbGet Command: Smarter Than You Might Think

If there's one thing that makes navigating a UNIX command line or tool console more…

• 1 min read
dbGet , tab completion , screencast , encounter , Digital Implementation , Encounter Digital Implementation

Digital Design

Five-Minute Tutorial: Fixing SI Victim Nets

It's hard to believe there was a time when we didn't even run signal integrity analysis…

• 2 min read
SI , EDI , SI victim nets , SI analysis , NanoRoute , encounter , victim nets , Signal Integrity , Digital Implementation , five minute

System, PCB, & Package Design 

Cadence OrCAD Capture Marketplace -- The Cool Factors

Hey, did you hear about the new Cadence OrCAD Capture Marketplace? It has the first…

• 2 min read
PCB , Marketplace , on-line store , OrCAD Capture Marketplace , applications , Capture CIS , OrCAD online store , Team OrCAD , OrCAD , apps

Verification

Panel Discussion: Applying High-Level Synthesis in an SoC Flow

Last Thursday, EETimes hosted a virtual System on Chip event focused on IP integration…

• 6 min read
IP , system on chip , BDTI , SoC , EETimes , Tensilica , Bluespec , SystemC , Synthesis , high level synthesis , HLS , C++ , ESL , System Design and Verification

Verification

Sometimes the Real World Needs Assertions Too

Every once in a while, I like to do a lightweight blog post linking my work world…

• 3 min read
ABV , asssertion-based verification , Functional Verification , formal , assertions

Verification

2011 CDNLive EMEA Highlights and Image Gallery: An EDA360 Spring Festival of Del…

Last week teammate Adam Sherer and I had the honor of representing the Incisive functional…

• 3 min read
RPP , Joe Hupcey III , Specman , Virtual System Platform , AVS , CDNLive , Functional Verification , Adaptive Voltage Scaling , Palladium , System Development Suite , EDA360 , VSP , Incisive , festival , Adam Sherer , Palladium XP , Philippe Magarshack , EMEA , Rapid Prototyping Platform , IEV , Incisive Enterprise Simulator (IES) , IES , Techcon , stmicroelectronics , IES-XL

Digital Design

Five-Minute Tutorial: Setting Up Clock Routing Rules

Hi, and welcome back to another Five-Minute Tutorial! Yes, I know it's been a while…

• 3 min read
EDI , clock routing , Routing , tutorial , encounter , Shielding , clocks , .ctstch , Digital Implementation , five-minute

System, PCB, & Package Design 

Miniaturization Through Embedded Packaged Components

As consumers we are very familiar with product miniaturization trends. We demand…

• 2 min read
PCB , PCB Layout and routing , IC Packaging and SiP Design , embedded components , PCB PI , IC Packaging , PDN , PCB Signal and power integrity , Power Integrity , PCB power integrity , Allegro 16.5 , TeamAllegro , High-Density Interconnect , miniaturization , PCB design , SPB16.5 , Allegro PCB Editor , HDI , Allegro

Verification

Free Webinar This Thursday: Rapid Design Bring-Up Using Formal and Simulation To…

Allow us to shamelessly promote a free webinar (including a live demo) this Thursday…

• 2 min read
Joe Hupcey III , ABV , CDNLive , Functional Verification , Metric Driven Verification , Formal Analysis , formal , webinar , SVA , Chris Komar , Silicon Realization , PSL , coverage driven verification (CDV) , assertions , MDV , IEV , Formal verification , Assertion-based verification

Verification

System Development Suite - Connecting Software to Hardware Design and Verificati…

I've been at CDNLive! EMEA watching demos of the newly announced System Development…

• 2 min read
ECO , Virtual System Platform , TLM , hardware , System Design and Verification , C-to-Silcon , System Development Suite , software , SystemC , verification

Verification

Yes We Can...Do FPGA-Based Prototoyping

As part of this week's System Development Suite announcement , Cadence introduced…

• 2 min read
RPP , Verification Computing Platform , prototyping , rapid prototyping , System Development Suite , Palladium XP , FPGA-based , Rapid Prototyping Platform , prototype , FPGA

Analog/Custom Design

Virtuoso Analog Design Environment XL – Embrace the Productivity

In my last blog, Virtuoso IC 5.1.41 was Good but Virtuoso IC6.1 is Better , I wrote…

• 4 min read
parasitic-aware design , Analog Design Environment , PAD , Virtuoso IC6.1.5 , Analog Simulation , analog , IC 6.1.5 , ADE , ADEnalog , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , Parasitic analysis , Custom IC Design

Verification

Welcome to the Cadence Virtual System Platform

The announcement of the Cadence Virtual System Platform is a momentous event for…

• 6 min read

Verification

Why Can’t You Write My Assertions for Me? - Part 3

My last two posts have dealt with various forms of automatic assertion creation…

• 2 min read
conformal , ABV , Zocalo , Functional Verification , formal , CPF , CDC , Palladium , Incisive , assertion synthesis , assertions , Constraints , IEV , Formal verification , IFV , Assertion-based verification
CDNS - Fix Layout Hompage