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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Blog - Post List
Latest blogs

Verification

It's Not Too Early to Think About DAC 2009

Even though it's still a couple of months off, it's not too early to think about…

• 1 min read
DAC 2009 , System Design and Verification , hardware-dependent software

Verification

OSCI Launches Video Tutorials for TLM 2.0

Cadence is one of the sponsors of a series of Open SystemC Initiative (OSCI) TLM…

• less than a min read
Intel , System Design and Verification , OSCI , TLM 2.0 , SystemC , interoperability , Modeling

Analog/Custom Design

Jurassic Park IV: The Return of ANALOG

In the lab, no one can hear you scream! When I was getting my BSEE in the…

• 2 min read
analog , Incisive , encounter , Virtuoso , RF design , Custom IC Design

Digital Design

EDA Industry Stays Ahead of Technology Curve

The EDA Industry is the unsung hero behind for modern era electronic revolution since…

• 2 min read
DAC , EDI , Multi-Core , Virtuoso , Parallel rocessing , Digital Implementation , DFM

Digital Design

Interview with SiRF's Nigel Foley on Low-Power Design

Over the last three years, customers have been able to leverage the Cadence Low-Power…

• 4 min read
digital Implementationg , Low Power , encounter 8.1 , Low-Power , encounter , Logic Design , Digital Implementation , Encounter Digital Implementation , Encounter Digital Implementation System 8.1

Analog/Custom Design

An Efficient and Fast Verification Flow for Analog Designs Validation using Virtuoso…

The emergence of sub-micron technologies has enabled today’s designers to include…

• 1 min read
CDNLive , Virtuoso , Spectre , RF design , MDL

Verification

Using Macros for Repetitive Coding Tasks

For this post welcome guest blogger Hilmar van der Kooij. Hilmar is a Cadence Application…

• 5 min read
Specman , Functional Verification , tech tips , OVM , OVM e , Coverage-Driven Verification , team specman , Aspect Oriented Programming , macros , AOP

SoC and IP

Early Returns on 1Q09 Financials

Memory Companies Suffer More in 1Q09, but Future Looks Better...or so they say: …

• 4 min read

RF Engineering

Enhanced pnoise Algorithm to Compute Phase-Noise for VCOs with Bandgap Voltage R…

Accurate phase-noise characterization is critical in the design of RF and microwave…

• 1 min read
DC , MMSIM , IC Voltage , RF design , VCO

Verification

Some SystemC Perspectives - An Interview with Vincent Motel

I sat down with Vincent Motel recently, a long time Cadence employee, and one of…

• 7 min read
OVM , C-to-Silicon , System Design & Verification , SystemC: OCSI

System, PCB, & Package Design 

What's Good About Relational Table Support in Capture-CIS? You'll Need SPB16.2 to

With SPB16.2 release, Capture-CIS allows you to create and use relational tables…

• 2 min read
SPB 16.2 , Functional Verification , Capture-CIS , RDBMS , Allegro

Analog/Custom Design

Getting a Feel for RF

It was a delight when I read the blog by Bill Schweber of TechOnline's RF DesignLine…

• 2 min read
MMSIM , Virtuoso Analog Design Environment , Virtuoso , RF design , Circuit Design , Simulators , Custom IC Design

SoC and IP

Industry Downturn Perspectives..Forward and Backward

Recent Results Signal Better Times Ahead; How Much Better?...Little Consensus,…

• 9 min read

Verification

Performance-Aware e Coding Guidelines – Part 5

In this last segment of the series on performance-aware coding, allow me to share…

• 2 min read
IEEE 1647 , performance , events , Specman , Functional Verification , API , tech tips , OVM , OVM e , e , temporal expressions , OVM-e , specman elite , IES , IES-XL

RF Engineering

2009 RFIC Symposium in Boston - Are You Going?

If you are an RFIC designer then I hope you are planning on attending the 2009 RFIC…

• 2 min read
RFIC , Virtuoso Spectre Simulator XL , spectreRF , Spectre , RF design , Circuit Design , harmonic balance , wireless integrated circuit verification

Digital Design

VoltageStorm Is Alive and Kicking!

If your only news source were some of the common EDA pundits, you would likely believe…

• 2 min read
timing system , ets , voltagestorm , EPS , Digital Implementation , encounter power system

Digital Design

WiMAX and the Road to Complete Independence From Network Cables: Sequans Communication…

Step into any Starbucks hotspot or Wi-Fi cafe, and you'll see something that was…

• 3 min read
Low Power , encounter 8.1 , Power-Efficient Design , SoC-Encounter" , Cadence Encounter Power System , Digital Implementation , The Power Forward Initiative , Encounter Digital Implementation , Encounter Digital Implementation System 8.1

Verification

Quick Tip - New Home For the "SVM" Docs

FAQs: What happened to the "SVM" documentation, and to SVM in general? Has SVM been…

• 1 min read
IPCM , Functional Verification , OVM , SVM , Incisive , eRM

System, PCB, & Package Design 

What's Good About Social Networking? Boomer Adoption up, Gen Y Flat

I decided to switch gears a bit and write about an interesting article I read in…

• 1 min read
social networking , Baby Boomers , PCB design , Generation Y , EE Times
CDNS - Fix Layout Hompage