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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

Verification

High-Level Design and Verification: How Can We Finally Move on From the Forrest Gump…

Richard Goering wrote an excellent summary of the DAC panel "High Level Synthesis…

• 3 min read
DAC , TLM , DAC panel , high-level verification , RTL , Forrest Gump , high-level design , SoC , System Design & Verification , SystemC , C-to-Silicon Compiler , high level synthesis , HLS , C++ , ESL , verification

Digital Design

EDI System’s get_metric Command Makes Metrics Reporting Quick and Easy

In this blog post I want to highlight the command get_metric that was introduced…

• 3 min read
get_metric , SoC-Encounter , cadence.com community , cadence , EDI system , EDI 11.1 , Cadence Online Support , encounter , EDI 10.1 , Digital Implementation , Encounter Digital Implementation , SoC Realization , EDI 11 , "SoC-Encounter"

Verification

Video: DAC 2012 Discussion with EET's Brian Fuller on EDA and Video

Continuing our conversation on leveraging social media for EDA, at the Design Automation…

• 1 min read
Brian Fuller , Joe Hupcey III , interview , video , Blogging , Social Media , DAC 2012 , EE Times

Verification

Video: Oski Technology’s Courageous "72 hour Verification Challenge" Using Incisive…

I've seen a lot of intriguing promotions over the years, but at DAC 2012 our partners…

• 1 min read
DAC , Joe Hupcey III , ABV , Functional Verification , bugs , NVIDIA , formal , Vigyan Singhal , Oski Technology , assertions , DAC 2012 , IEV , Formal verification , IFV , verification , Assertion-based verification

Verification

DAC 2012 Best User Track Paper Review: Deploying Model Checking for Bypass Verif…

Bypass logic verification is a common and difficult challenge for modern VLSI design…

• 3 min read
DAC , ABV , DAC best paper , Functional Verification , formal , Vigyan Singhal , bypass verification , bypass logic , User Track , papers , DAC 2012 , IEV , Darrow Chu , Formal verification

Analog/Custom Design

Tech-On-Tour: Bringing Advanced Mixed-Signal Design Methodology from Concepts to…

About a year ago, Cadence offered a worldwide Tech-On-Tour (ToT) series for mixed…

• 1 min read
DAC , Technology on tour , mixed-signal methodology , tech on tour , CPF , Mixed-Signal , encounter , Virtuoso , Cortex-M0 , incyte , mixed signal , Mixed-Signal Methodology Book , tech-on-tour , OpenAccess

System, PCB, & Package Design 

What's Good About ADW’s Bulk Editing? Check out the 16.5 Release and See!

The 16.5 Allegro Design Workbench (ADW) release provides bulk editing support. This…

• 1 min read
PCB , Allegro Design Workbench , Library flow , Library and design data management , bulk editing , SPB , design data management , PCB design , SPB16.5 , Librarians , library , ADW , Schematic

Verification

Photo Essay and Comments on DAC 2012 in San Francisco, CA

In addition to the annotated image gallery (click here or on the image), below are…

• 3 min read
gallery , DAC , Joe Hupcey III , ABV , CDNLive , Functional Verification , formal , "Coverage Unreachability" , formal apps , Richard Goering , 20nm , Vigyan Singhal , bypass verification , Denali Party , UCIS , DVcon , Accellera , Lego , Hosted Design Solutions , DAC 2012 , robot , IEV , Oski , Rubik's Cube , Formal verification , IFV , cloud computing , verification

SoC and IP

Martin Lund on the Future of IP (Video Interview)

As SoC complexity continues to rise, more IP is being utilized, and the quality and…

• less than a min read
IP , Martin Lund , video , IP integration , Lund , Live Stream , future of IP , EE Times

Verification

Using Event Ports (With Edge Attribute) to Define Simulator Sensitive Events Rather…

There are two ways in e to define an event to be sensitive to a change of value in…

• 6 min read
AF , events , Specman , Synchronization , Functional Verification , event ports , ports , simple ports , e language , team specman , interface , edge attribute

System, PCB, & Package Design 

What's Good About Object Visibility Layers in DEHDL? The Secret's in the 16.5 Release

In the 16.5 Design Entry HDL (DEHDL) release, Object Visibility Layers are introduced…

• 1 min read
PCB , Allegro Design Entry , hierarchy , DEHDL , object visibility layers , hierarchical schematics , PCB Editor , Design Entry HDL , Front-end PCB design , design , PCB design , Design Entry , SPB16.5 , ConceptHDL , PCB Capture , Schematic , Allegro

RF Engineering

Measuring Bipolar Transistor ft with Fixed Base-Collector Voltage

Recently I had a question from reader. He asked a good question: "How do you to measure…

• 2 min read
RF , RF Simulation , fixed base-collector voltage , parametric analysis , RFIC , bipolar transistor , measuring bipolar transistor ft , Schaldenbrand , analog , ADE , Vbc , Virtuoso , ViVA , RF design , transistor ft , testbench

System, PCB, & Package Design 

What's Good About PCB SI PDN Analysis? 16.5 Has Many New Enhancements!

As clock and data frequencies increase and high-speed systems become more densely…

• 4 min read
PCB SI , PCB , SI , PI , SiP , PCB PI , PDN , Signal Intregrity , Digital SiP design , SigXP UI , PCB Signal and power integrity , Power Integrity , High Speed , PCB power integrity , Allegro 16.5 , SPB , Power Delivery Network , full wave , Signal Integrity , full-wave , PDN Analysis , "PCB design" , field solver , PCB Signal integrity , Allegro PCB SI , PCB design , "PCB PI" , SPB16.5 , Allegro PCB Editor , SI analysis and modeling , "Power Delivery Network" , Predictable PCB design , Allegro

Verification

DAC 2012: Connecting Emulation to the Real World of Wireless Interfaces

This is certainly the most connected DAC I have been to so far. Tweets and connections…

• 2 min read
ESL Market , DAC , wireless , Verification Computing Platform , Virtual System Platform , software virtual prototype , cadence , Acceleration , Functional Verification , Palldium XP , System Design and Verification , System Development Suite , system modeling , embedded software , Rohde & Schwarz , Emulation , dac2012 , LTE , Design Automation Conference , carrier aggregation , LTE advanced

Verification

DAC 2012: High-Level Synthesis Tutorial Standing Room Only

Monday is tutorial day at DAC, and this year the highest-attended tutorial was Synthesizing…

• less than a min read
High-Level Synthesis , Intel , C to Silicon , dac2012 , Bohm , SystemC , Synthesis , HLS , ESL , verification

Verification

DAC 2012 Gary Smith EDA Kickoff: EDA and ESL Growth and Four Different Software Virtual…

DAC 2012 kicked off yesterday with the annual DAC Reception followed by Gary Smith…

• 3 min read
ESL Market , DAC , Virtual System Platform , software virtual prototype , cadence , Functional Verification , System Design and Verification , Gary Smith EDA , System Development Suite , system modeling , embedded software , GSEDA , dac2012 , Design Automation Conference

Verification

DAC 2012: Handling a Double Paradigm Shift for Embedded Software Development

Change is hard. And we in product marketing for development tools are trying to cause…

• 4 min read
DAC , Virtual System Platform , CDNLive , cadence , debug , Functional Verification , Verum , System Design and Verification , Methods2Business , System Development Suite , system modeling , embedded software , dac2012 , Technology Adoption , Software Generation , Design Automation Conference , Formal verification

Verification

Accellera Systems Initiative Releases UVM 1.1b for SystemVerilog

Accellera Systems Initiive released the UVM 1.1b on its website June 1 and announced…

• less than a min read
DAC , uvm , uvm world , Functional Verification , UVM 1.1b , Accellera

Verification

Being The Energizer Bunny at DAC … Championing System-Level Design and Verification…

As the EDA industry and its customers are preparing for the yearly show down at the…

• 19 min read
NextOp , DAC , CDNLive , debug , Functional Verification , LeCroy , AMD , System Design and Verification , celeration , Methods2Business , System Development Suite , Xilinx SDK , Incisive , in-circuit emulation , LSI , Palladium XP , Emulation , in-circuit acceleration , Dini , Imperas , ARM , Design Automation Conference , Rohde&Schwarz , DAC breakfast
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