Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

The Facts: Why Accelerated VIP Is Needed for SoC Verification

On Tuesday May 15 th Cadence announced the expansion of our VIP Catalog to include…

• 4 min read
AVIP , SystemVerilog , accelerated VIP , Verification IP , uvm , Acceleration , Functional Verification , VIP , Palladium , Palladium XP , Emulation , VIP Catalog , simulation VIP , ACE verification , e language , SCE-MI , SystemC , protocol verification , simulation , verification

Digital Design

Adding Custom Shapes and Text is New and Improved in EDI System 11

You may have noticed that in the Encounter Digital Implementation (EDI) System 11…

• 4 min read
dbGet , add_shape , custom text , custom shapes , add_text , EDI 11.1 , digital implementation , Encounter Digital Implementation , OpenAccess , EDI 11

Verification

American Technology Awards - Finally I Can Explain to my Mom What I am Actually Working…

I think all of us engineers have faced at one point or another the need to explain…

• 2 min read
Rapid Protoytping Platform , Virtual System Platform , virtual platforms , awards , Watson , virtual prototypes , American Technology Awards , Jeopardy , System Development Suite , VSP , Incisive , Palladium XP , Raritan , Mother's Day , System Design and Verification , cloud computing , FPGA-based prototyping

Verification

DAC 2012 Preview: Focus on Formal and ABV Events and Papers

In a few short weeks DAC 2012 will be upon us (June 3-7, 2012 in San Francisco, CA…

• 2 min read
DAC , Incisive Formal Verifier , ABV , Functional Verification , Formal Analysis , formal , "Coverage Unreachability" , coverage unreachability , formal apps , model checking , bypass verification , apps , Lego , User Track , assertions , papers , DAC 2012 , robot , IEV , Design Automation Conference , Rubik's Cube , IFV , Assertion-based verification

Verification

Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage…

Memory management is not something the Specman user is supposed to worry about. Nobody…

• 9 min read
AF , Specman , Memory , garbage , Functional Verification , garbage collection , Specman garbage collection , Incisive , e language , managing memory , Specman data , memory errors , testbench , simulation , memory management , verification

Verification

Video Tech Tip: Data Path Verification Using a Formal Scoreboard with Incisive Formal…

This 6 minute video is a quick overview of our formal scoreboard app. Specifically…

• less than a min read
scoreboard , ABV , Joerg Mueller , Formal Analysis , formal , video , formal apps , apps , formal scoreboard , IEV , IFV

System, PCB, & Package Design 

What's Good About Allegro PCB Router HDI Capabilities? 16.5 Has a Few New Enhancements

More high-density interconnect (HDI) improvements including the tuning of the auto…

• 1 min read
PCB , PCB Layout and routing , interconnects , inset vias , Routing , via tangency , Allegro 16.5 , via rules , PCB Editor , High-Density Interconnect , Layout , via , via patterns , design , vias , PCB design , SPB16.5 , HDI , microvia , Allegro

System, PCB, & Package Design 

Free PCB Signal Integrity Education from Robert Hanson Continues at Cadence in A…

Over fifty PCB enthusiasts ascended upon the Cadence campus in Austin, Texas last…

• 1 min read
PCB SI , PCB , SI , DDR2 , transmission line , PCB PI , PDN , Austin , Robert Hanson , "PCB SI" , PCB power integrity , Allegro 16.5 , IBIS-AMI , Power Delivery Network , Signal Integrity , PCB Signal integrity , Allegro PCB SI , PCB design , "PCB PI" , PCI Express , "Power Delivery Network" , DDR3 , Allegro

Verification

Xilinx Zynq-7000 Virtual Platform Performance: Native Linux vs. VirtualBox

In my last blog post , I covered three frequently asked questions about using the…

• 5 min read
taskset , virtual platforms , Unity 2D , System Development Suite , embedded software , VSP , Ubuntu , VirtualBox , virtual prototype , Virtual Machine , Linux vs VirtualBox , Unity3D , xilinx , graphics , linux , Zynq-7000 , simulation , ESL , System Design and Verification

Verification

Xilinx Zynq-7000 Virtual Platform Frequently Asked Questions: VirtualBox Edition

The use of virtual machine technology offers great ease of use benefits. Since the…

• 7 min read
VBoxManage , port forwarding , network address translation , eclipse , virtual platforms , NAT , virtual prototypes , embedded software , Xilinx SDK , Ubuntu , VirtualBox , system design , Virtual Machine , FAQ , System Design & Verification , xilinx , Zynq virtual platform , Zynq-7000 , ESL

Digital Design

Five-Minute Tutorial: Understanding the Encounter Power System (EPS) Reports Dir…

No matter how you run your power analysis - with Encounter Power System (EPS) or…

• 3 min read
EDI , rail analysis , EPS reports , tutorial , encounter digital implementation system , EPS , encounter , digital implementation , IRdrop , Power Analysis , powergrid view , EM , five-minute , encounter power system , electromigraion

Analog/Custom Design

What is Digitally Assisted Analog Design?

Mixed-signal applications are among the fastest growing segments in the electronics…

• 2 min read
daa , AMS , Low Power , mixed signal design , mixed signal solution , Mixed-Signal , dac2012 , Mixed signal physical implementation , mixed signal , cortex M , DAC 2012 , ARM , boris murmann , digitally assisted analog , mixed-signal verification

System, PCB, & Package Design 

What's Good About Allegro Via Patterns During Group Routing? See for Yourself in…

New to the 16.5 release of Allegro PCB Editor is the ability to establish via patterns…

• 3 min read
PCB , PCB Layout and routing , blind vias , diff pairs , inset vias , global route , Routing , staggered vias , layer stacks , Allegro 16.5 , SPB , via rules , PCB Editor , High-Density Interconnect , Layout , via , via patterns , design , vias , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , differential pairs , group routing , Differential Pair Support , buried vias , HDI , PCB Capture , Allegro

Verification

My Constraint was Ignored – Is it a Tool Bug? IntelliGen Gen Debugger Can Help!

The IntelliGen Gen Debugger is a powerful Specman tool that can debug any generation…

• 4 min read
AF , IntelliGen , Specman , debug , Functional Verification , Gen debugger , test generation , Gen , Generation , e language , Constraints , constraint not enforced , verification

System, PCB, & Package Design 

What's Good About OrCAD Capture’s Find Result Report? Look to SPB16.5 and See!

The OrCAD Capture 16.5 release now has a method to generate a report (in CSV or HTML…

• 1 min read
PCB , capture , "capture CIS" , Allegro Design Entry , Design Entry CIS , OrCAD Capture Marketplace , Find command , OrCAD Capture , Capture CIS , Capture-CIS , Allegro 16.5 , SPB , Find result , design , OrCAD , PCB design , Design Entry , SPB16.5 , PCB Capture , Schematic , OrCAD reports

System, PCB, & Package Design 

What's Good About ADW’s Generic Models? Check out the 16.5 Release and See!

The 16.5 release of Allegro Design Workbench ( ADW ) provides support for generic…

• 1 min read
PCB , generic models , Allegro Design Workbench , Library flow , Allegro 16.5 , Library and design data management , design data management , design , "PCB design" , PCB design , SPB16.5 , Librarians , library , ADW , Allegro

Verification

Analyzing Error Reports When Specman Crashes

One of the most frustrating events while running a tool would be to experience a…

• 8 min read
AF , SystemVerilog , Specman , OVM ML , Functional Verification , Testbench simulation , OVM e , EDA , e , stack trace , Signal Integrity , e language , team specman , Aspect Oriented Programming , eRM , specman crashes , simulation , AOP , IES-XL

Verification

Video: “Drive For Innovation” Finds It At Every Turn

With some notable exceptions, too often technology trade press reporting has been…

• less than a min read
Brian Fuller , Avenet Express , Joe Hupcey III , innovation , "Drive for Innovation" , UBM Electronics , Chevy Volt , EE Times

Verification

Modeling Large Memories in SystemC

Sometimes Virtual Platforms model systems with large amounts of memory. Many embedded…

• 3 min read
zynq , Memory , virtual platforms , TLM , virtual prototypes , SDRAM , Verilog , SystemC memories , SystemC , memory models , modeling memories , linux
CDNS - Fix Layout Hompage