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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Analog/Custom Design

How Fred Discovered Mixed-Signal Behavioral Modeling

Introduction This is the first of a series of blogs where we will add pieces to the…

• 3 min read
AMS , mixed signal design , AMS-Designer , Verilog-AMS , analog , Mixed-Signal , Virtuoso , Fred , assertions , mixed signal , wreal

Analog/Custom Design

A Moment to Mourn -- John McCarthy, Father of Lisp

Here lies a Lisper Uninterned from this mortal package Yet not gc'd While we…

• 1 min read
John McCarthy , McCarthy , software development , Lisp , Custom IC Design , SKILL

Verification

Welcome to the Zynq-7000 Virtual Platform

As you might guess we are pretty excited about the Virtual Platform development for…

• 4 min read
zynq , virtual platforms , TLM , EPP , Zynq-7000' , virtual prototypes , Cortex-A9 , System Design and Verification , software , SystemC , xilinx , ARM , linux , extensible , FPGA

Verification

Verification and the Need for Collaboration

Earlier this week I was at the ARM TechCon in Santa Clara, a show that gets better…

• 2 min read
NextOp , ARM Techcon , uvm , collaboration , Zocalo , Functional Verification , Standards , partnerships , VA , EDA360 , EDA , Duolog , verification alliance , UCIS , AMIQ

Verification

Report: Formal Analysis Papers at CDNLive India 2011

On October 19, 2011 in Bangalore, India more than 800 engineers across all domains…

• 3 min read
ABV , CDNLive , Functional Verification , Formal Analysis , ABVIP , formal , Lokesh Pundreeka , ADS , metric-driven verification , assertions , MDV , IEV , Assertion-Driven Simulation , Formal verification , IFV , India , Assertion-based verification

System, PCB, & Package Design 

What's Good About PCB SI IOCell Editor in Model Editor? 16.5 Has a Few New Enhancements

There are currently multiple options for model editing in the Allegro PCB SI environment…

• 2 min read
PCB SI , PCB , SI , I/O , SiP , Signal Intregrity , Digital SiP design , SigXP UI , PCB Signal and power integrity , High Speed , Allegro 16.5 , SigWave , Signal Integrity , Allegro PCB SI , PCB design , SPB16.5 , IOCell Editor , SI analysis and modeling , model editor , library , Allegro

Verification

Virtual Platform UART Use Number 4: Connecting to an RTOS Tracing Framework

This is the last installment of my series on different uses for the UART in Virtual…

• 4 min read
Virtual System Platform , virtual platforms , Quantum Platform , virtual prototypes , dining philosophers , UART , System Design and Verification , RTOS tracing , QP , software , qspy

Verification

Come See How to Connect SystemVerilog and SystemC Using UVM

All pun-tastic references aside, connecting SystemVerilog and SystemC is becoming…

• 1 min read
SystemVerilog , uvm , OVM ML , Functional Verification , webinar , multi-language , SystemC , IES

System, PCB, & Package Design 

What's Good About APD’s Die Abstract Compare? You’ll Need the 16.5 Release to See

In the distributed co-design environment in the SPB16.5 Allegro Package Designer…

• 4 min read
PCB , SiP , IC Packaging , packaging , SiP Design , APD , Allegro 16.5 , IC/package co-design , PCB Editor , Allegro Package Designer , Layout , design , PCB design , die abstract compare , SPB16.5 , die abstract , Allegro

Analog/Custom Design

SKILL for the Skilled: Introduction to Classes -- Part 3

In the previous posting Introduction to Classes -- Part 2 we saw the high level…

• 8 min read
Team SKILL , programming , Sudoku , classes , IC 6.1.5 , object orientation , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL

Verification

Too Many Missing Real-World Assertions?

Well, here I am embarking on my fifth post in which I point out illogical situations…

• 4 min read
ABV , Functional Verification , formal , assertions , Assertion-based verification

System, PCB, & Package Design 

Team Allegro to Preview PCB 3D Full-Wave Technology at EPEPS 2011

At the Electrical Performance of Electronic Packaging and Systems conference ( EPEPS…

• 1 min read
PCB , UIUC , EMS2D , EPEPS , interconnects , PCB PI , packaging , 3D extraction , PCB Signal and power integrity , Signal Integrity , full-wave , Allegro PCB SI , PCB design , EM , EMS3D , DDR3 , Allegro

Verification

Formal Verification with Asynchronous Clocks

Many designs have multiple independent clock inputs with different frequency specifications…

• 2 min read
ABV , asssertion-based verification , Joerg Mueller , Verification methodology , Functional Verification , Formal Analysis , formal , SVA , PSL , assertions , IEV , Formal verification , IFV , verification

System, PCB, & Package Design 

What's Good About Allegro GRE Disabling Bundle Compression? It’s in the 16.5 Release

With the SPB16.5 release of Allegro Global Route Environment (GRE) , you can now…

• 1 min read
PCB , PCB Layout and routing , bundle compression , global route , Routing , Allegro 16.5 , PCB Editor , Layout , design , PCB design , SPB16.5 , Allegro PCB Editor , GRE , disabiling bundle compression , Allegro

Verification

Automating UVM to Tackle Insidious HW/SW Bugs

You've just sat through a 2-hour program review. The 30 minutes you spent describing…

• 1 min read
SystemVerilog , uvm , bugs , Duolog , universal verification methodology , Accellera VIP TSC , David Murray , IES

RF Engineering

Guidelines for Maximizing Speed vs Accuracy for Harmonic Balance - Part 1

Greetings, I am often asked for guidelines on maximizing speed vs. accuracy for SpectreRF…

• 2 min read
RF , RF Simulation , analog/RF , APS , HB , Spectre RF , Analog Simulation , Virtuoso Spectre Simulator GXL , ADE , Virtuoso Spectre Simulator XL , spectreRF , RF design , harmonic balance

System, PCB, & Package Design 

What's Good About Allegro PCB Router HDI Via Tangency? Check Out 16.5!

High Density Interconnect (HDI) techniques are increasing in the PCB domain. HDI…

• 1 min read
PCB , blind vias , global route , Routing , layer stacks , High Speed , via tangency , Allegro 16.5 , PCB Editor , High-Density Interconnect , Layout , via , design , miniaturization , PCB design , SPB16.5 , Allegro PCB Editor , buried vias , HDI , microvia , Allegro

Verification

Free Webinar Thursday 10/13 -- Automating Assertion Generation for Simulation, Formal…

Everyone can agree that Assertion-Based Verification (ABV) is a powerful methodology…

• 1 min read
NextOp , Joe Hupcey III , ABV , methodology , interview , Formal Analysis , BugScope , Incisive , webinar , DVcon , assertion synthesis , assertions , IEV , Yuan Lu , Formal verification , IFV , Assertion-based verification , IES-XL

Verification

17M Gates in 8 Months with 2 Designers -- What is Your ROI for Higher-Abstraction…

In their presentation at the recent SystemC Japan conference, Renesas Micro Systems…

• 3 min read
time-to-market , High-Level Synthesis , verification turnaround , TLM , C-to-Silcon , ROI , System-Level Design , SystemC , C-to-Silicon Compiler , productivity
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