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Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
• 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
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Blog - Post List
Latest blogs

Breakfast Bytes

COTS? Commercial Products in US Government Electronics

COTS is government jargon for Commercial Off-The-Shelf. This means the government…

• 8 min read
us government , minsec , department of defense

The India Circuit

Four Exciting Examples of Modern AI from NVIDIA

A few months ago, we had the honor of having Vishal Dhupar, Managing Director of…

• 4 min read
artificial intelligence , deep learning , NVIDIA , machine learning , AI

Analog/Custom Design

Virtuosity: SKILLful Virtuoso Visualization and Analysis

If you’re a SKILL enthusiast, you’ll be happy to know that the latest IC6.1.7 ISR…

• 4 min read
Analog Design Environment , ViVa-XL , custom/analog , Analog Simulation , SKILL for the Skilled , ADE , Virtuoso , ViVA , Virtuosity , Custom IC Design , SKILL , Cusstom IC Design

Breakfast Bytes

IEDM 2017

The start of December means it is the International Electron Devices Meeting in San…

• 6 min read
Intel , copper beol , 3D IC , AMD , georgia tech , Samsung , TSMC , fanout wafer packaging , GlobalFoundries

Analog/Custom Design

Virtuosity: Can I Graphically Edit Width Spacing Patterns?

We have enhanced the editing modes available for WSPs. In addition to the text-based…

• 1 min read
Routing , Advanced Node , width spacing patterns , Layout , Virtuoso , Virtuosity , Custom IC Design

Academic Network

2017 Workshop on Electronic Design Automation in Tainan Taiwan

It was the third continuous year that Cadence Academic Network supported the Workshop…

• 1 min read
Taiwan , Cadence Academic Network , EDA

Breakfast Bytes

Greg Yeric and Rob Aitken Dive into the Details

The last day of TechCon had two keynotes rich in deeper technical content, from Greg…

• 6 min read
security , greg yeric , graphen , IoT , trillion devices , Rob Aitken , more than Moore , moore's law , power

Breakfast Bytes

Advanced Packaging Delivers More Than Moore

Moore's Law is running out of steam. Depending on your point of view, it is dead…

• 8 min read
FOWLP , advanced packaging , 3DIC , Virtuoso , OrbitIO , Innovus , 2.5D , Allegro

Digital Design

Get Early Silicon Learning to Accelerate Yield Ramp-up

How important is it for your advanced node products to get early silicon learning…

• 2 min read
DNA , pattern analysis , machine learning , silicon learning , yield , test chip , design for manufacturing , DFM

Whiteboard Wednesdays

Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 2

In this week's Whiteboard Wednesday, Tom Hackett continues his explanation of neural…

• less than a min read
Whiteboard Wednesdays , neural networks

Analog/Custom Design

Virtuosity: Can I Plot Signals with Different Axis Units in the Same Window?

Have you been frustrated trying to drag signals around in Virtuoso Visualization…

• 1 min read
virtuoso visualization and analysis , Virtuoso Analog Design Environment , Analog Design Environment , ViVA

Breakfast Bytes

Supercomputers

HPC, or high-performance computing, is one of the big focus areas for semiconductors…

• 9 min read
Intel , top 500 list , top500 , supercomputer

Analog/Custom Design

Virtuosity: CDNLive India—Our Window to KYC!

In line with the recently-implemented mandate in India requiring banks and financial…

• 1 min read
CDNLive India 2017 , Cadence Help Future , Virtuosity , Virtuoso Video Diary , Cadence Help 3.0

Breakfast Bytes

What's For Breakfast? Video Preview December 11th to 15th 2017

https://youtu.be/Ar98HS9Dnow Coming from Union Square, San Francisco (camera Carey…

• less than a min read
government , risc-v , International Electron Devices Meeting , cots , risc-v workshop , Aviation , IEDM

SoC and IP

Book Your CES Meetings Now!

Want to see the exciting technology that is behind some of the biggest innovations…

• 1 min read

Breakfast Bytes

Formal Verification Sign-Off...and the First Text Message

Recently, it was the 10th annual Jasper User Group meeting (see my earlier post Jasper…

• 8 min read
Jasper User Group , JUG , formal , Oski Technology , Formal verification

RF Engineering

How to Set Up and Plot Large-Signal S Parameters?

Large-signal S-parameters (LSSPs) are an extension of small-signal S-parameters and…

• 1 min read
RF Simulation , Spectre RF , Virtuoso ADE , Virtuoso

Verification

Perspec System Verifier is #1 in Portable Stimulus in 2017 User Survey

It’s now official: Perspec System Verifier is rated the #1 product in the #1 category…

• 3 min read

Breakfast Bytes

Silexica: Mastering Multicore

Since the invention of the microprocessor, it was a dream that it would be possible…

• 9 min read
silexica , Tensilica , multicore
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