Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
• 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

Jasper User Group: How to Be a Formal Verification Lead

Recently, it was the 10th annual Jasper User Group meeting (see my earlier post Jasper…

• 7 min read
Intel , Jasper User Group , JUG , formal , verification

RF Engineering

Triple Beat Analysis: What, Why & How?

The Triple Beat analysis is similar to Rapid IP2/IP3 analysis except that it uses…

• 2 min read
Virtuoso ADE , Virtuoso , Spectre , RF design

The India Circuit

Hello, My Name Is Anna. Can I Help You?

Chatbots are annoyingly familiar to anyone who has shopped online. The distracting…

• 3 min read
chatbot , artificial intelligence , Wysa , AI

Verification

Check Again: Cadence Announces Release of the First PCIe 5.0 VIP—With TripleCheck…

On November 28, 2017, Cadence announced the release of the first available PCIe®…

• 1 min read
Functional Verification , PCI-e , announcement , TripleCheck

Breakfast Bytes

Chips and Technologies: The First Fabless Company

As part of writing Fabless: the Transformation of the Semiconductor Industry a couple…

• 5 min read
fabless , chips and technologies , foundry

Breakfast Bytes

November Breakfast Buffet

https://youtu.be/paqvuLll4pM Coming from the rain on the roof of Cadence building…

• less than a min read
Jasper User Group , Rutenbar , breakfast buffet , JUG , Kaufman Award , fabless , alto , chips and technologies , social engineering

Whiteboard Wednesdays

Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 1

In this week's Whiteboard Wednesday, Tom Hackett explains neural network basics using…

• less than a min read
Whiteboard Wednesdays , neural networks

Breakfast Bytes

CCIX Update: TSMC, Xilinx, Cadence, Arm...and Jasper

CCIX (pronounced see-six) is the Cache Coherent Interconnect for Accelerators. I…

• 5 min read
Jasper User Group , JUG , formal , ccix , TSMC , xilinx , ARM

RF Engineering

Measuring Rapid IP3

In the world of analog design, IP3—the third order intercept point, is a known parameter…

• 1 min read
RF Simulation , Rapid IP3 , spectreRF

Breakfast Bytes

What's For Breakfast? Video Preview December 4th to 8th 2017

https://youtu.be/LcmP8GkqvEw Coming from outside on the Cadence campus (camera…

• less than a min read
ARM Techcon , Jasper User Group , supercomputers , more than Moore , 3D packaging , ARM , IEDM

Breakfast Bytes

What's the Difference Between MOESI and MESI? Cache-Coherence for Poets

Increasingly, a lot of SOCs contain multicore processors, multiple separate processors…

• 9 min read
moesi , cache-coherent interconnect , formal , cache-coherence , cache , JasperGold , mesi , Formal verification

Digital Design

Cadence Modus DFT at International Test Conference 2017

While DAC is the focal point for the EDA industry, the test community travels in…

• 1 min read
Automotive , DFT , modus , ATPG , diagnostics , ITC

Verification

26262 4U: Infineon and the Incisive Functional Safety Simulator

Infineon and Cadence have a bit of a history: they’ve been working together on functional…

• 2 min read
Infineon , Functional Verification , fault , ifss

Breakfast Bytes

What You See Isn't Always What You Get

I wrote earlier in the week, in my post The Alto—Forty Years On , about the origin…

• 3 min read
thanksgiving , off-topic , illusion

System, PCB, & Package Design 

A Peek into the Future of Signal Integrity with Artificial Neural Networks

Imagine how great life could be if computers or robots can do all our tedious work…

• 6 min read
PCB , EPEPS , DDR4 , deep learning , adaptive equalizers , ANN , Artificial Neural Networks , neurons , activation function , training , coefficients , machine learning , Signal Integrity , DDR , Sigrity , backchannel propagation , SystemSI

The India Circuit

Will Artificial Intelligence Take Over Art Forms?

In February last year, San Francisco’s art lovers were treated to a new kind of exhibition…

• 2 min read
DeepDream , artificial intelligence , project magenta , AI , Nsynth

Analog/Custom Design

Virtuosity: Organizing Waveform Families

When plotting waveforms in Virtuoso Visualization and Analysis across sweeps you…

• 2 min read
ADE GXL , ADE Explorer , ADE XL , ADE , Virtuoso Analog Design Environment , Analog Design Environment , ViVA , Virtuosity , ADE Assembler

Breakfast Bytes

The Alto—Forty Years On

I talked yesterday about the history of the Xerox PARC Alto machine, which is a computer…

• 6 min read
icarus , alto , xerox , PARC , wysiwyg

System, PCB, & Package Design 

How Can I Assess Process Variation in My IC Package Design?

In a previous blog we talked about the IC Packaging Design Variant tool. As you recall…

• 2 min read
SiP , design variants , IC package design , APD , manufacturing , 17.2
CDNS - Fix Layout Hompage