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Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
• 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
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Blog - Post List
Latest blogs

Verification

Accelerating the Next Big Shift in Verification

Today Cadence announced that we are aligning our proposal to the Accellera Portable…

• 5 min read
pswg , scenario , UML , software-driven verification , Accellera

Whiteboard Wednesdays

Whiteboard Wednesdays - Addressing SoundWire Design Challenges

In this week's Whiteboard Wednesdays video, the second in a two-part series, Charles…

• less than a min read
Design IP , Whiteboard Wednesdays , software design challenges , MIPI SoundWire

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Line Width Retention? 16.6 Has It!

Currently, user line width overrides are permitted during the Add Connect command…

• 1 min read
PCB Layout and routing , 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro

System, PCB, & Package Design 

Integrate PVS into Your IC Package Design Flow to Optimize for Manufacturability…

As package substrates continue to get more complex, often resembling silicon as much…

• 4 min read
IC Packaging and SiP Design , GDSII , DRC , stream , 16.6 , SPB , PVS

SoC and IP

USB Type-C Ecosystem, Issues, and Opportunities

USB Type-C is an innovation that is transforming the electronics industry. What is…

• less than a min read
USB Type-C , DisplayPort , MCCI , Alternate Mode

Whiteboard Wednesdays

Whiteboard Wednesdays—The Applications and Benefits of 802.11ad

In this week's Whiteboard Wednesdays video, Bob Salem provides a detailed overview…

• less than a min read
wireless , Whiteboard Wednesdays , 802.11x , 802.11ad

Digital Design

Five-Minute Tutorial: Innovus Clock Tree Synthesis and Debugger

Hi Everyone, Last time, our Five-Minute Tutorial focused on the new Innovus Placement…

• less than a min read
training , ccopt , clock tree synthesis , debugger , Digital Implementation , Innovus

SoC and IP

Cadence IP for USB Works over Type-C (Proof Inside)

There is no other specification in the history of USB that caused so much discussion…

• 1 min read
USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Whiteboard Wednesdays

Whiteboard Wednesdays - Evolution of Automotive Electronics

In this week's Whiteboard Wednesdays, Charles Qi talks about the evolution of electronics…

• less than a min read
Whiteboard Wednesdays , IP , functional safety , infotainment , automotive electronics , Tensilica , ADAS

System, PCB, & Package Design 

What's Good About Allegro PCB Editor NC Route? 16.6 has Several New Enhancements…

There are a few NC Route enhancements in the 16.6 Allegro PCB Editor release. Read…

• 1 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , Routing , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays—Managed NAND Flash Devices

In this week's Whiteboard Wednesdays video, Lou Ternullo provides a detailed overview…

• less than a min read
Whiteboard Wednesdays , IP , NAND flash , system design

SoC and IP

Electrical Validation of DDR4 Interfaces

Developing SoCs with high-speed memory interfaces, such as DDR4, presents substantial…

• 1 min read
Design IP , DDR4 , LPDDR , DDR , Sigrity , Tektronix

SoC and IP

Cadence ONFI 4.0 Flash Memory IP Increases Data Access to 800Mtps and Reduces Power…

Announcing Availability of ONFI 4.0 IP Flash memory applications have expanded…

• 2 min read
QSPI , flash , ONFI , USB , SD , eMMC , ip cores , ECC

System, PCB, & Package Design 

Manage Your Shapes with Ease in the Latest 16.6 ISR of Cadence APD and SiP Layou…

Shapes. Whether it’s a split plane, a power ring or flag under your die, or a cavity…

• 4 min read
IC Packaging and SiP Design , Cadence Design Systems , bounding shapes , Digital SiP design , degassing , 16.6 , beta tools , package design , SiP Layout , shapes , application modes

System, PCB, & Package Design 

What's Good About Allegro PCB Editor DRC by Window? It’s in the 16.6 Release!

The 16.6 Allegro PCB Editor ‘DRC by Window’ command is an alternative to running…

• 1 min read
PCB , Cadence Design Systems , Allegro GUI , Allegro 16.6 , electrical constraints , SPB , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays—More on Camera Subsystems

In this week's Whiteboard Wednesdays video, the second in a three-part series, Pulin…

• less than a min read
blocks , Whiteboard Wednesdays , IP , subsystem , intellectual protocol , Tensilica , camera

Verification

Double-Take: Improving Validation Test Suite with System-Level, Coverage-Driven …

Application Spotlight When Freescale wanted to measure the coverage of their validation…

• 2 min read
validation test suite , Freescale , Coverage-Driven Verification , Palladium XP , verification

Whiteboard Wednesdays

Whiteboard Wednesdays - LPDDR4 for Automotive Memory

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty discusses why LPDDR4…

• less than a min read
Automotive , Whiteboard Wednesdays , IP , Memory , LPDDR4

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Disable of Open Space Routing? 16.6 Has It!

By default, the 16.6 Allegro PCB Editor ‘Add Connect’ command generates routes when…

• 1 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , Routing , SPB , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro
CDNS - Fix Layout Hompage