Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Digital Design

Cadence RTL Design Studio: Built for the Full PPAC Journey

If you've used Joules RTL Design Studio, you already know what it can do. Now it…

raquelp
• 2 min read
Digital Design and Signoff , featured , Joules , Digital Implementation , rtlstudio

Corporate News

How the New ASK AI Assistant Makes Support More Seamless

Finding the right answer often takes more than one question. Users may start with…

Corporate
• 2 min read
featured , customer support , Generative AI , ASK Portal , ASK AI Assitant

Artificial Intelligence (AI)

You'll Still Do the Work—You Just Won't Do the Boring Part

Agentic AI is about to change your flow. Here's what actually shifts—and why the…

Corporate
• 5 min read
artificial intelligence , featured , agentic ai , NVIDIA , AI for design

Artificial Intelligence (AI)

The Feedback Loop Is the Moat

Every verification and design team I talk to is building agents right now. The demos…

HS202601273724
• 14 min read
featured , AI in chip design , GenAI , AI/ML
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Digital Design

Cadence: Committed to DFM

On June 10, Cadence issued a press release that mentioned “…decreasing the level…

• 1 min read
Advanced Node , Mixed-Signal , encounter , Virtuoso , Manufacturability sign-off , Digital Implementation , DFM

SoC and IP

Unity's New CMOx Memory Technology Appears on Horizon

Summary: Unity Semiconductor has come forth recently with a new candidate for Storage…

• 7 min read

Verification

Send Us Suggestions for Updating the e/Specman Quick Reference Card

Team Specman is about to start a project to refresh the e /Specman Quick Reference…

• less than a min read
Specman , Tech Pubs , Functional Verification , e , team specman , Incisive Enterprise Simulator (IES) , IES-XL

Verification

Speeding up SystemC compilation with Incisive SystemC

If you’re a C++ and SystemC programmer you know that when you’ve spent all day tracking…

• 6 min read
System Design and Verification , OSCI , embedded software , Incisive , SystemC analysis , George Frazier , System Design & Verification , SystemC , SystemC: OCSI , ESL

Digital Design

Technical Webinars Hosted by the Experts - Don't Miss Them!

Starting June 23, 2009, Cadence technical experts will host a series of technical…

• 1 min read
Low Power , webinars , advanced design , design planning , Digital Implementation , physical implementation , timing convergence

SoC and IP

Taiwan Agonistes: Why Taiwan Should Demote DRAMs, and Agressively Expand Its Foundry…

Taiwan Cannot Shake Attraction for DRAMs, Marches Down Same Path as Many Others Before…

• 13 min read

Verification

VCS Runs OVM -- 2 Years Late, But Welcome None the Less

Something seems to have changed in the Synopsys VCS simulator; the Web2.0 world is…

• 1 min read
SystemVerilog , OVM Professionals Network , Functional Verification , OVM , Incisive , PSL , IES , OVMWorld

Verification

New Video on "Metric Driven Verification 101", With Yours Truly Giving the Intro

Recently I had the honor of delivering the introductory section of a detailed demo…

• 1 min read
Verification methodology , metric driven verification (MDV) , Functional Verification , Coverage-Driven Verification , Enterprise Manager

Verification

Tip for Linking AMIQ’s DVT to the Specman Docs

Since posting an introductory article and demo on AMIQ’s “DVT” integrated development…

• 2 min read
Specman , Tech Pubs , Functional Verification , tech tips , Incisive , AMIQ , Incisive Enterprise Simulator (IES) , IES-XL

System, PCB, & Package Design 

What's Good About the new FPGA System Planner? - Ask Hemant Shah!

Our product marketing manager for Allegro PCB products, Hemant Shah introduced the…

• 2 min read
FPGA System Planner , FSP , PCB design , FPGA

Verification

OVM Metric Driven Verification With an FPGA-based Design

During the last 2 years I have enjoyed the opportunity to work with the Incisive…

• 2 min read
System Design and Verification , OVM , Incisive , System simulation and analysis , ISX , Hardware/software co-verification , FPGA

Analog/Custom Design

Things You Didn't Know About Virtuoso: Managing Your Real Estate - Part 2

I keep my toothpaste in my bathroom. I keep the paprika in the kitchen. I keep the…

• 2 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

The DWARF Debugging File Format

The Chronicles of Narnia has always been one my favorite series of books. Today,…

• 7 min read
System Design and Verification , DWARF , ARM , ELF , debugging

Verification

Enabling OVM Transaction Debug in SimVision Without Code Changes

Are you tired of putting print statements in your code to do debug? Do you work…

• 5 min read
SystemVerilog , debug , Functional Verification , simvision , OVM SV , OVM 2.0 , IES , IES-XL

Verification

Team genIES Bloggers Create Simulation Magic

Simulation is a huge topic. Performance, debug, mixed-signal, low-power, assertions…

• 1 min read
Functional Verification , Incisive , OV , IES , IES-XL

Verification

Tips on Using “vhdlsync” With e+Mixed HDL Simulation

[ Team Specman welcomes Principal Support Application Engineer Avi Farjoun to share…

• 3 min read
AF , Specman , Functional Verification , tech tips , Incisive , e , Verilog , multi-language , Incisive Enterprise Simulator (IES) , VHDL , IES , IES-XL

Verification

Thoughts on the DVClub Talk: "Is it Time to Declare Verification War?"

As noted in a prior post , I had the pleasure of attending a DVClub talk given by…

• 2 min read
verification strategy , metric driven verification (MDV) , Functional Verification , DVClub , MDV

Analog/Custom Design

Things You Didn't Know About Virtuoso: Managing Your Real Estate - Part 1

Yeah, right...in this economy, don't talk to me about real estate. But I'm not talking…

• 3 min read
real estate , Virtuoso , assistants , Custom IC Design

Verification

Heads-up: Mixed Signal Verification Webinar (June 10)

For those Specmaniacs using the REAL number data type & ports capabilities in Specman…

• 1 min read
AMS , Specman , verification strategy , Functional Verification , Incisive , e , Incisive Enterprise Simulator (IES) , verification , IES-XL
CDNS - Fix Layout Hompage