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SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About ADW’s Pull-Down Lists? 16.6 Has a Few New Enhancements!

The 16.6 Allegro Design Workbench (ADW) release now provides the ability to customize…

• 2 min read
Cadence Design Systems , Allegro 16.6 , cadence , DBeditor , 16.6 , property , Allegro Design Workbench , Library flow , selection filters , Library and design data management , SPB , design data management , Front-end PCB design , design , PCB design , Design Entry , Grzenia , Librarians , library , ADW , Allegro

SoC and IP

Intel Developer Forum (IDF13): A "Look Inside" the Technology Showcase

The recent Intel Developer Forum 2013 in San Francisco was notable for the sheer…

• 3 min read
Intel , IDF13 , Design IP , IP , Rajkumar Chandrashekhar , Gen3 , cadence , Intel Developer Forum , MIPI , M-PCIe , Arif Khan , MPCIe , Mahesh Wagh , PCIe , interoperability , PCI Express

SoC and IP

IEEE 802.3 -- Standardizing the Next Generation of Ethernet PHYs

I attended the IEEE 802.3 standards meeting in York, England recently. Over 200 people…

• 1 min read
Design IP , 802.3bs , PHY , 400Gpbs , 40Gbps , Automotive Ethernet , 100Gbps , IEEE 802.3 , Ethernet , Marris , semiconductor IP , Ethernet PHYs , data centers

Digital Design

Five-Minute Tutorial: EM Model Files Revisited

Back in January, I posted a Five-Minute Tutorial about creating EM Model files .…

• 2 min read
EDI , qrcTechFile , EM Model , ICT , Techgen , iRCX , EPS , digital implementation , EM Model File , Power Analysis , EM , five minute tutorial

Analog/Custom Design

Virtuosity: 15 Things I Learned in August by Browsing Cadence Online Support

Our folks over in Physical Design have been busy churning out helpful Rapid Adoption…

• 3 min read
Rapid Adoption Kit , Virtuoso , Spectre , Virtuosity

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Shape Contraction and Expansion? Check Out 16

The 16.6 Allegro PCB Editor includes new enhancements to effectively manage shape…

• 3 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , cadence , 16.6 , PCB Editor , Layout , design , PCB design , Grzenia , physical layout design , Allegro PCB Editor , Allegro , etch shapes

System, PCB, & Package Design 

Create Optimum Pin Assignments for FPGAs on PCBs - Part 2 of 2

In part 1 of this blog , I discussed a scenario that PCB designers working with FPGA…

• 5 min read
FPGA: ASIC Prototype , FPGA-PCB Co-Design , FPGA System Planner , FPGAs , FSP , pinswap , "PCB design" , OrCAD , PCB design , pin planning , pin swap , FPGA , Allegro , FPGA Pin Assignment , FPGA: PCB

Verification

HDMI 2.0 – Ushering in the Next Generation of Ultra HD TV

The future of television is being defined by two key technologies: organic light…

• 2 min read
Verification IP , HDMI 2.0 , Ultra HD , 4K TV , cadence , VIP , HDTV , SoCs

Analog/Custom Design

SKILL for the Skilled: Visiting All Permutations

In this posting I want to look at several ways of generating permutations of a list…

• 8 min read
Team SKILL , programming , Jim Newton , IC615 , SKILL for the Skilled , permutations , Lisp , SKILL++ , SKILL

System, PCB, & Package Design 

How Do You Route Your Highly Constrained PCBs? (Part 1 of 2)

How routing is performed to meet the design intent of designers and engineers seems…

• 4 min read
interface aware design , DDR2 , Constraint-driven PCB Design flow , interconnects , Allegro 16.6 , Routing , route quality , 16.6 routing , interface definitions , interfaces , PCB Editor , PCB routing , Allegro router , "PCB design" , PCB design , Constraint Driven PCB routing , DDR3

Analog/Custom Design

SKILL for the Skilled: How to Copy a Hash Table

In this posting I want to look at ways to copy a hash table in SKILL. There are several…

• 8 min read
Team SKILL , programming , hash table , Jim Newton , IC615 , SKILL for the Skilled , Lisp , SKILL++ , SKILL

Verification

Configurable Specman Messaging Webinar Archive Available Now

Configurable Specman Messaging for Improved Productivity Webinar Archive Available…

• 1 min read
IEEE 1647 , Specman/e , AVS , Functional Verification , Specman e , Testbench simulation , Incisive Enterprise Simulator , e-language , configurable messaging , EDA , e , webinar , e language , Specman messaging , Specman C

System, PCB, & Package Design 

Create Optimum Pin Assignments for FPGAs on PCBs - Part 1 of 2

In most FPGA-based boards, the PCB designer is on his own -- with little help from…

• 5 min read
FPGA: ASIC Prototype , FPGA-PCB Co-Design , FPGA System Planner , FPGAs , FSP , pinswap , "PCB design" , PCB design , pin planning , pin swap , FPGA , FPGA Pin Assignment , FPGA: PCB

System, PCB, & Package Design 

What's Good About FSP’s Allegro PCB Editor Board Import? 16.6 Has It!

The Allegro FPGA System Planner (FSP) has the ability in the 16.6 release to import…

• 5 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro 16.6 , cadence , FPGA-PCB Co-Design , FPGA System Planner , 16.6 , Taray , FPGAs , SPB , PCB Editor , Layout , design , FSP , "PCB design" , PCB design , Grzenia , Allegro PCB Editor , FPGA , Allegro , FPGA: PCB

System, PCB, & Package Design 

Enhance Your Packaging Documentation Outputs with the New SKILL Spreadsheet API Tools…

Spreadsheets, we all use them, and many of us do so daily. They are an efficient…

• 3 min read
IC Packaging and SiP Design , SiP , IC Package , IC Packaging , packaging , Digital SiP design , 16.6 , IC Packaging and SiP , IC package design , APD , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , APD 16.6 , SiP Layout , IC Package Physical layout and co-design , cavity

Verification

Getting Ready for ESL with Emulation!

Next week on Monday, August 19th, Gary Smith will run a webinar called " ESL - Are…

• 2 min read
Low Power , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , cadence , Acceleration , System to Silicon Verification , Dynamic Power Analysis , System Design and Verification , System Development Suite , embedded software , Gary Smith , GSEDA , Palladium XP , Emulation , Atrenta , Schirrmeister , ESL , low power optimization

Analog/Custom Design

Virtuosity: 16 Things I Learned in July by Browsing Cadence Online Support

Feeling a bit lazy this month, but even without digging too deeply, I could find…

• 2 min read
AMS , mixed-signal simulators , custom/analog , Virtuoso Space-based Router , Routing , Rapid Adoption Kit , MMSIM , Mixed-Signal , Virtuoso , Schematic Editor , Virtuosity , AMS simulation , mixed signal , Modeling , Custom IC Design , space based router

System, PCB, & Package Design 

What's Good About Allegro PCB Enhanced Object Filtering? See for yourself in 16.6

The 16.6 Allegro PCB Editor release provides enhanced Object Filtering to control…

• 2 min read
PCB , PCB Layout and routing , Cadence Design Systems , diff pairs , constraint databases , Allegro GUI , Allegro 16.6 , cadence , DEHDL , electrical constraints , object visibility layers , 16.6 , property , diff pair , SPB , PCB Editor , Constraint Manager , Design Entry HDL , differential pair , Layout , Xnets , design , "PCB design" , PCB design , Design Entry , Constraints , Grzenia , Allegro PCB Editor , differential pairs , Differential Pair Support , ConceptHDL , PCB Capture , Allegro

System, PCB, & Package Design 

What's Good About AMS Schematic Undo? It’s in the 16.6 Release!

Just a very brief post this week on a new AMS Simulator (PSpice) capability. The…

• less than a min read
capture , AMS , Allegro 16.6 , cadence , AMS simulator , OrCAD Capture , 16.6 , Capture CIS , PSPICE , OrCAD , AMS simulation , Grzenia
CDNS - Fix Layout Hompage