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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

Analog/Custom Design

Things You Didn't Know About Virtuoso: Outputs Setup in ADE XL

Continuing on our exploration of ADE XL (see here and here for previous articles…

• 5 min read
IC 6.1 , Analog Simulation , analog , ADE , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , ADE-XL , IC 6.1.4 , Custom IC Design

System, PCB, & Package Design 

What's Good About Capture Objects Look and Feel? You Can Change Them in SPB16.3!

The SPB16.3 release of Allegro Design Entry CIS (known as Capture) has some cool…

• 2 min read
"capture CIS" , SPB16.3 , Allegro Design Entry , Capture CIS' , Design Entry CIS , OrCAD Capture , Allegro 16.3 , SPB 16.3 , Capture CIS , Capture-CIS , SPB , design , Design Entry , PCB Capture , Schematic

SoC and IP

Kingston DDR3 RAM cracks 3Gtransfers/sec barrier, achieves 3.068 Gtransfers/sec amid…

Mix liquid nitrogen and Kingston’s HyperX DDR3-2333 SDRAM modules and you get 3068…

• 1 min read

Digital Design

CDNLive! Silicon Valley Abstract Deadline Extended 1 Week

The deadline for submitting abstracts to CDNLive! Silicion Valley 2010 has been extended…

• less than a min read
CDNLive!

Verification

System Realization Webinars Start Sept 8th

Starting September 8th Cadence will be hosting a series of webinars about various…

• 2 min read
TLM , webinars , system realization , Calypto , Imperas , CircuitSutra , XtremeEDA , ESL

SoC and IP

OCZ accentuates the positive (SSDs) and eliminates the negative (low-margin DRAM…

PC add-on vendor OCZ has announced today that its future is in SSDs and high-speed…

• 1 min read

Verification

Performance Tips and Tricks: Another Specman Performance Series

Building on the great success of Efrat Shneydor's previous blog series, Performance…

• 1 min read
performance , Specman , Functional Verification , Testbench simulation , EDA , e , team specman , Aspect Oriented Programming , AOP

Verification

Report On Chelsio’s DAC Case Study In Formal Verification

As the leader of the Formal Verification R&D team, I'm always fascinated by the many…

• 2 min read
DAC , ABV , verification strategy , Functional Verification , Formal Analysis , formal , Incisive , IFV

SoC and IP

Embedded SSDs: SanDisk’s iSSD puts 64Gbyte SATA SSD on a BGA device measuring only…

The convenience of SSDs that look like HDDs is that they can seamlessly plug and…

• 1 min read

SoC and IP

Steve Wozniak talks about the importance of memory in system design

Last week at the Flash Memory Summit, Steve Wozniak gave a keynote presentation where…

• less than a min read

SoC and IP

SSDs versus HDDs: Comments on that giant, yellow, flashing, caution light

A couple of weeks ago, I noted the continued disparity between SSD and HDD pricing…

• 2 min read

Digital Design

Webinar: SOI Gives More Performance Per Watt, And There's An Easy Path

If you've seen any of the recent buzz lately around Silicon-On-Insulator (SOI),…

• less than a min read
Low Power , webinars , Low-Power , Power-Efficient Design , Digital Implementation , Silicon on Insulator , Power Analysis , mixed signal , SOI , power

SoC and IP

NAND Flash in Space: JPL’s Strauss reports advanced Flash devices with finer geometries…

Yesterday, I blogged about a presentation on embedded SSDs given at the Flash Memory…

• 5 min read

Verification

Inside The Virtual File System

As part of my ongoing effort to report and explain interesting topics related to…

• less than a min read
virtual file system , DS-5 , system , software , Virtual Platforms , ARM

SoC and IP

SSD Form Factors: Viking Modular Solutions talk at Flash Memory Summit explodes the…

Everyone “knows” what an SSD looks like. It looks just like an HDD, usually in a…

• 3 min read

System, PCB, & Package Design 

What's Good About Deleting Parts in ADW? You Can Easily Do This In ADW16.3!

Part, Schematic, Footprint and Models can all be deleted from the database now with…

• 3 min read
SPB16.3 , data management , DEHDL , PTF , DBeditor , Allegro 16.3 , SPB 16.3 , property , Allegro Design Workbench , Library flow , SPB , Design Entry HDL , design , PCB design , Design Entry , ADW 16.3 , Allegro PCB Editor , Librarians , ConceptHDL , library , ADW , Allegro

Analog/Custom Design

Analog Design vs. Automation -- Why Are They At Odds?

Back in 2002 and 2003 there was a lot of talk about analog synthesis being the …

• 2 min read
IC 6.1 , Bleasdale , analog , ADE , Virtuoso Analog Design Environment , optimization , Virtuoso , ADE-GXL , ADE-XL , Parasitic analysis , Circuit Design , Custom IC Design

SoC and IP

Andy Walls of IBM talks about NAND Flash for Enterprise Applications

Just got back from a morning spent at the Flash Memory Summit. The last talk I listened…

• 2 min read

SoC and IP

Intel’s SSD roadmap starts appearing on the Web

Any company in the SSD business knows it must face Intel, so there’s always wide…

• less than a min read
CDNS - Fix Layout Hompage