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Featured

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
Corporate 8 Oct 2025 • 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか?」をテーマに、本田技術研究所社 先進技術研究所(HGRX)との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
Cadence Japan 8 Oct 2025 • less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
Sheryl G 7 Oct 2025 • 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
Corporate 2 Oct 2025 • 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

Verification

Software Development Tool Teardown For The Motorola Droid

Lately, device teardowns of consumer electronics have become popular. There are many…

jasona 19 Jul 2010 • 4 min read
ADB , GDB , android , QXDM , DDMS , JTAG , ETM , vnc , Monkey , QPST , Systemm Verification

Verification

More Thoughts On How To Choose Between The OVM And The UVM

There has been a lot of on-line discussion since DAC about whether the Universal…

tomacadence 16 Jul 2010 • 2 min read
uvm , OVM , VIP , EDA , Accellera , Mentor

SoC and IP

AnandTech analyzes Crucial C300 SSD with Marvell controller in “The SSD Diaries.…

Anand Lal Shimpi, the man behind the AnandTech.com Web site, has published an extended…

archive 14 Jul 2010 • less than a min read

Verification

Changing the Status Quo in SoC to System Hand-off

As part of EDA360 Cadence is learning how to play a more significant role in the…

jasona 13 Jul 2010 • 4 min read
Device Drivers , virtual platforms , Droid

SoC and IP

MemCon 2010 looms (July 28). Huge networking opportunity with big list of attendees…

Memcon 2010 is a little more than two weeks away and although we’ve blogged about…

archive 12 Jul 2010 • 1 min read

SoC and IP

Upgrading Old PCs with SSDs: Where’s the Notion of Balance?

Martin Veitch of the UK’s www.CIO.co.uk online magazine recently wrote a blog that…

archive 9 Jul 2010 • 4 min read

SoC and IP

SSDs in embedded control: cold rolling steel in old European factories, Part 2, now…

Back in May, the Denali Memory Report covered an industrial application for SSDs…

archive 8 Jul 2010 • 1 min read

SoC and IP

Flash Memory Summit looms in August: All things Flash

When we weren’t looking, registration for MemCon zoomed past 500 and it’s still climbing…

archive 8 Jul 2010 • 1 min read

SoC and IP

Virident PCIe SSD delivers 320,000 read IOPS with 24-year service life

Add Virident to the growing list of companies that have introduced SSDs in the form…

archive 7 Jul 2010 • 1 min read

Verification

Why The UVM Is Ready For Production Use Today -- Part 3

This is the final installment of my blog posts based on the three common questions…

tomacadence 7 Jul 2010 • 1 min read
uvm , Verification methodology , OVM , VIP , Accellera VIP TSC

Verification

Duolog Interview At DAC 2010, And The IP Integration Aspect Of EDA360

One virtue of events like DAC is that is provides an open forum for vendors to show…

jvh3 7 Jul 2010 • less than a min read
Cadence Connections , DAC , uvm , IP , IP-XACT , OVM , EDA360 , Duolog

SoC and IP

Specialty semiconductor foundry TowerJazz licenses “Y-Flash” IP to “leading” digital…

TowerJazz, the specialty semiconductor foundry created by the merger of Tower Semiconductor…

archive 6 Jul 2010 • 2 min read

System, PCB, & Package Design 

What's Good About Via DRCs In Allegro Constraint Manager? It's In SPB16.3!

Current design technologies require extremely tight matching requirements right down…

Jerry GenPart 2 Jul 2010 • 1 min read
PCB , PCB Layout and routing , SPB16.3 , Allegro 16.3 , SPB 16.3 , SPB , PCB Editor , Constraint Manager , via , "PCB design" , PCB design , Allegro PCB Editor

SoC and IP

Will Taiwan Innovation Memory Company (TIMC) become Taiwan’s NAND Flash Inc?

The Taiwan Innovation Memory Company (TIMC) was originally formed as the Taiwan Memory…

archive 1 Jul 2010 • 1 min read

Verification

Why The UVM Is Ready For Production Use Today - Part 2

In my last blog post , I talked about the three most common questions I heard at…

tomacadence 1 Jul 2010 • 1 min read
DAC , uvm , OVM , VIP , EDA

SoC and IP

DRAM vendors look to 40nm process technology to keep DRAM profits flowing next y…

Taiwan Economic News reports that DRAM vendors will be bringing 4x nm process technologies…

archive 30 Jun 2010 • 1 min read

Verification

DAC Report: Interview With AMIQ And Update On Their “DVT” IDE

One of the benefits of the Design Automation Conference is the opportunity to follow…

jvh3 30 Jun 2010 • 1 min read
SystemVerilog , DAC , uvm , OVM ML , Functional Verification , OVM , EDA360 , e , OVM-e , Verilog , AMIQ , VHDL

Verification

DAC report: Video Interview With Zocalo

One of the benefits of the annual Design Automation Conference is the opportunity…

TeamVerify 29 Jun 2010 • 1 min read
DAC , ABV , Functional Verification , Formal Analysis , EDA360 , EDA , SVA , IEV , IFV

Verification

Why The UVM Is Ready For Production Use Today - Part 1

As I mentioned in my DAC report , I spent the largest percentage of my time at the…

tomacadence 29 Jun 2010 • 2 min read
DAC , uvm , Functional Verification , OVM , VMM
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