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Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Analog/Custom Design

Five Reasons I'm Excited About Mixed-Signal Verification in 2015

Key Findings : Many more design teams will be reaching the mixed-signal methodology…

• 7 min read
uvm , mixed signal design , Metric-Driven-Verification , Mixed Signal Verification , MDV-UVM-MS

Whiteboard Wednesdays

Whiteboard Wednesdays—Consumer DRAM Trends

In this week's Whiteboard Wednesdays video, Lou Ternullo explains the DRAM trends…

• less than a min read
Whiteboard Wednesdays , DDR4 , DRAM , DDR3

Whiteboard Wednesdays

Whiteboard Wednesdays—Selecting the Right DDR PHY Solution

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty reviews evaluation…

• less than a min read
Whiteboard Wednesdays , IP , Floorplanning , PHY IP , DFI

Analog/Custom Design

Mixing It Up in Hardware (an Advantest Case Study in Faster Full-Chip Simulations…

Key Findings: Advantest, in mixed-signal SoC design, sees 50X speedup, 25 day test…

• 9 min read
Advantest , Palladium , Mixed Signal Verification , Emulation , mixed signal

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Select by Lasso or Path? 16.6 Has It!

The 16.6 Allegro PCB Editor release contains two new selection options, lasso and…

• 1 min read
PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , cadence , Routing , route quality , bulk editing , SPB , PCB Editor , PCB design , Allegro PCB Editor

Whiteboard Wednesdays

Whiteboard Wednesdays—TripleCheck VIP

In this week's Whiteboard Wednesdays video, Moshik Ruben discusses TripleCheck verification…

• less than a min read
Verification IP , Whiteboard Wednesdays , IP , VIP , TripleCheck

System, PCB, & Package Design 

Multi-Fabric Planning for Efficient PCB Design

Recently, an article was published in Printed Circuit Design and Fab about Multi…

• 1 min read
BGA-style package , PCB design , multi-fabric planning , pin assignment

Analog/Custom Design

Virtuosity: A Very Large Number of Things I Learned in September and October 2014…

There has been a flurry of activity on COS over that past couple of months. I can…

• 8 min read
AMS , MMSIM , Advanced Node , ADE XL , Virtuoso , Analog Design Environment , Custom IC Design , Virtuoso Layout Suite XL , IC 6.1.6

Verification

Where Is the Money for IoT?

I attended the Gartner Semiconductor briefing on Oct. 23, 2014, the theme of which…

• 1 min read
Verification IP , DSP , IP , IoT , Tensilica , always-on

System, PCB, & Package Design 

Do You Design Wafer-Level Chip-Scale Packages? Cadence 16.6 SiP Layout Makes Your…

As these types of designs see an increasing number of applications and design starts…

• 4 min read
IC Package , SiP Design , Co-Design , layout pin numbering

Analog/Custom Design

The Elephant in the Room: Mixed-Signal Models

Key Findings: Nearly 100% of SoCs are mixed-signal to some extent. Every one of these…

• 5 min read
metrics-driven methodology , real number modeling , uvm , CPF , RNM , UPF , mixed signal , MDV , verification

Whiteboard Wednesdays

Whiteboard Wednesdays—Verification IP Productivity Tools

In this week's Whiteboard Wednesdays video, Tom Hackett talks about Cadence Verification…

• less than a min read
Verification IP , Whiteboard Wednesdays , VIP , PureView , productivity , TripleCheck

SoC and IP

Its Name is C, Type-C: The New Superhero of Cables from USB

Isn’t it interesting how, with time, all the nitty-gritty of technology is starting…

• 2 min read
Design IP , IP , Jacek Duda , USB , ip cores , USB3.0

Verification

Generic Dynamic Runtime Operations With e Reflection - Part 3: Additional Capabilities…

This post concludes the series of blog posts that discuss the dynamic capabilities…

• 3 min read
AF , Specman , debug , Functional Verification , Incisive , e language , reflection , simulation

Verification

Transferring e "when" Subtypes to UVM SV via TLM Ports—UVM-ML OA Package

The UVM-ML OA (Universal Verification Methodology - Multi-Language - Open Architecture…

• 5 min read
AF , uvm , Specman , debug , Functional Verification , Incisive , UVM ML , e language , simulation

Verification

Generic dynamic run-time operations with e reflection Part II

Field access and method invocations In the previous blog , we explained what are…

• 4 min read
AF , Functiional Verification , e language , Funcional Verification , coverage driven verification (CDV) , Aspect Oriented Programming , reflection

Analog/Custom Design

It’s Late, But the Party is Just Getting Started

Key Findings: Many more chip programs are crossing the tipping point and need advanced…

• 6 min read
AMS , analog behavior , AMS-Designer , AMS Designer , analog behavioral models , analog/mixed-signal , AMS Verification

SoC and IP

Call for Papers Now Open – CDNLive Silicon Valley

CDNLive Silicon Valley (March 10-11, 2015, Santa Clara Convention Center) provides…

• less than a min read
IP , EDA conference , CDNLive , IP papers , EDA papers

Whiteboard Wednesdays

Whiteboard Wednesdays—PCIe Controller Solution

In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan breaks down Cadence…

• less than a min read
performance , Whiteboard Wednesdays , PCIe , latency , PCI Express
CDNS - Fix Layout Hompage