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Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About Using Sigrity and Cadence SiP Digital to Reduce Design Costs? Check…

This week, you can view a couple of videos where customers describe how they used…

• 1 min read
SiP , Digital SiP design , Power Integrity , Layout , Signal Integrity , PCB design , Sigrity

Whiteboard Wednesdays

Whiteboard Wednesdays—Configurable 10/40G Ethernet Solution

In this week's Whiteboard Wednesdays video, Arthur Marris discusses configurable…

• less than a min read
Whiteboard Wednesdays , IP , Mac , 10/40G , Ethernet , SerDes , PCS

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Artwork Film Capabilities? 16.6 Has Several…

The 16.6 Allegro PCB Editor release contains several enhancement to the Artwork Film…

• 1 min read
PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , artwork , SPB , PCB Editor , Layout , design , PCB design , Allegro PCB Editor , Allegro

Digital Design

Five-Minute Tutorial: One More Look at EM Models

Just when you thought you were done setting up EM model files, along came another…

• 2 min read
Voltus , Digital Implementation , Power Analysis , EM , five minute tutorial

Whiteboard Wednesdays

Whiteboard Wednesdays—DDR Training Modes

In this week's Whiteboard Wednesdays video, Jeffrey Chung discusses the various training…

• less than a min read
Whiteboard Wednesdays , training , DDR , timing

System, PCB, & Package Design 

What's Good About Allegro PCB Editor New Slide Capabilities? 16.6 has Several New…

The 16.6 Allegro PCB Editor release's new ‘Slide’ command utilizes a move-intersect…

• 8 min read
PCB , PCB Layout and routing , interconnects , Allegro GUI , Allegro 16.6 , cadence , Routing , DRC , Placement Edit , diff pair , SPB , PCB Editor , High-Density Interconnect , Layout , Allegro router , PCB design , Spacing , Allegro PCB Editor

Whiteboard Wednesdays

Whiteboard Wednesdays—Choosing the Right NAND Flash Solution

In this week's Whiteboard Wednesdays video, Lou Ternullo walks you through the steps…

• less than a min read
Whiteboard Wednesdays , IP , NAND flash

Verification

Looking Back at a Great Week for System Design!

Reflecting on last week at ARM TechCon, together with our close partner ARM, we had…

• 3 min read
debug , System Design and Verification , embedded software , hybrid , ARM TechCon 2014 , ARM , verification

Verification

Cadence Palladium Platform and ARM Fast Models - Making the Future the Present

In its 10th year now, ARM TechCon is in full swing this week at the Santa Clara Convention…

• 3 min read
NVIDIA , Palladium , hybrid , Emulation , ARM Fast Models , ARM

Whiteboard Wednesdays

Whiteboard Wednesdays—Ethernet in Cars

In this week's Whiteboard Wednesdays, Arthur Marris introduces the next big thing…

• less than a min read
communication protocol , Automotive Ethernet , Ethernet , open standard , interoperability

Verification

Troubleshooting Incisive Errors/Warnings with nchelp/ncbrowse and Cadence Support…

I joined Cadence in July 2000 and was immediately put on a three-month training to…

• 4 min read
nchelp , Incisive , error , xcelium simulator , troubleshooting , mnemonic , xcelium , utilities , xmhelp

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Move Lines/Text to Different Classes? Check…

Beginning with the 16.6 Allegro PCB Editor release, lines and text can now be moved…

• 1 min read
PCB , Allegro 16.6 , SPB , PCB Editor , Layout , Grzenia , Allegro PCB Editor

Whiteboard Wednesdays

Whiteboard Wednesdays—Select the Right Performance for a 802.11ac/Advanced LTE A…

In this week's Whiteboard Wednesdays video, Priyank Shukla removes the mystery behind…

• less than a min read
wireless , Whiteboard Wednesdays , 802.11x , wireless AFE , analog front end , AFE , LTE

Digital Design

New Training Class: Get Up to Speed Fast When Migrating to Encounter Digital Implementation…

One question we often hear from experienced physical design engineers migrating to…

• 2 min read
P&R , encounter digital implementation system , place and route , Rapid Adoption Kits , RAKs , physical implementation

SoC and IP

IoT Focus: IoT Applications Require a New Architectural Vision

I wrote earlier that the sheer vastness and potential for IoT designs require a different…

• 3 min read
Consumer Electronics , IoT , IP integration , ip cores , Internet of Things , Seow Yin Lim , interface design , user interface

Whiteboard Wednesdays

Whiteboard Wednesdays - Formal VIP for 100% Accurate Designs

In this week's Whiteboard Wednesdays video, Tom Hackett discusses formal verification…

• less than a min read
Whiteboard Wednesdays , Formal Analysis , formal verification IP , formal VIP , Formal verification

SoC and IP

How Do You Build a Wi-Fi 802.11ac Programmable Modem?

The Tensilica® group at Cadence has just published a 37-page application note on…

• 1 min read
Wi-Fi 802.11ac transceiver , Tensilica DSPs , WLAN , LTE , programmable modem

System, PCB, & Package Design 

What's Good About Capture’s Design Rule Checks? 16.6 Has Several New Enhancements…

The Allegro Design Entry CIS (OrCAD Capture) 16.6 release provides extensions to…

• 1 min read
Design Rule Checker , Allegro 16.6 , Design Entry CIS , DRC , 16.6 , Capture CIS , SPB , OrCAD

System, PCB, & Package Design 

Have a Complex, Off-Grid Pin Pattern to Number? Cadence Allegro16.6 IC Package Design…

Complex dies with a mixture of digital and analog circuitry means equally complex…

• 4 min read
IC Packaging and SiP Design , IC Packaging , IC packaging SiP Layout , SiP Design , Digital SiP design , IC Packaging and SiP , layout pin numbering , IC packaging documentation , pin numbering , SiP Layout
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